reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
625 unsigned Opc = MI->getOpcode(); 629 if (MI->getOperand(1).getReg() != ARM::SP) { 630 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop)) 632 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); 635 unsigned Imm = MI->getOperand(2).getImm(); 641 if (!isARMLowRegister(MI->getOperand(0).getReg())) 643 if (MI->getOperand(3).getImm() != ARMCC::AL) 645 const MCInstrDesc &MCID = MI->getDesc(); 647 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) 651 BuildMI(MBB, MI, MI->getDebugLoc(), 651 BuildMI(MBB, MI, MI->getDebugLoc(), 653 .add(MI->getOperand(0)) 654 .add(MI->getOperand(1)) 659 MIB.setMIFlags(MI->getFlags()); 661 LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI 664 MBB.erase_instr(MI); 669 if (Entry.LowRegs1 && !VerifyLowRegs(MI)) 672 if (MI->mayLoadOrStore()) 673 return ReduceLoadStore(MBB, MI, Entry); 680 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { 684 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop)) 688 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); 699 if (MI->getOperand(2).getImm() == 0) 700 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); 705 if (MI->getOperand(1).isImm()) 706 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); 716 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, IsSelfLoop)) 718 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); 723 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) 727 if (MI->getOperand(0).isKill()) 728 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);