reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5386 if (!isARMLowRegister(Reg))
lib/Target/ARM/ARMConstantIslandPass.cpp1779 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { 1786 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {lib/Target/ARM/ARMFrameLowering.cpp
2057 isARMLowRegister(Reg) || 2092 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg))) {lib/Target/ARM/ARMLoadStoreOptimizer.cpp
731 if (isARMLowRegister(NewBase) && isARMLowRegister(Base) && 731 if (isARMLowRegister(NewBase) && isARMLowRegister(Base) &&lib/Target/ARM/AsmParser/ARMAsmParser.cpp
1637 return isARMLowRegister(Memory.BaseRegNum) && 1638 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1643 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1653 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1663 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 6550 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && 6551 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && 6577 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6578 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 6579 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || 6595 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6596 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 7159 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 9499 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9500 isARMLowRegister(Inst.getOperand(1).getReg()) && 9531 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9532 isARMLowRegister(Inst.getOperand(1).getReg()) && 9533 isARMLowRegister(Inst.getOperand(2).getReg()) && 9568 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9569 isARMLowRegister(Inst.getOperand(1).getReg()) && 9797 !isARMLowRegister(Inst.getOperand(0).getReg()) || 9946 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9967 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9968 isARMLowRegister(Inst.getOperand(1).getReg()) && 9990 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9991 isARMLowRegister(Inst.getOperand(1).getReg()) && 10084 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10085 isARMLowRegister(Inst.getOperand(2).getReg())) && 10119 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10120 isARMLowRegister(Inst.getOperand(2).getReg())) && 10217 isARMLowRegister(Inst.getOperand(1).getReg()) && 10218 isARMLowRegister(Inst.getOperand(2).getReg())) 10222 isARMLowRegister(Inst.getOperand(0).getReg()) && 10223 isARMLowRegister(Inst.getOperand(1).getReg()))lib/Target/ARM/Thumb1FrameLowering.cpp
379 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { 534 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {lib/Target/ARM/Thumb1InstrInfo.cpp
83 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && 87 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { 112 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && 116 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) {lib/Target/ARM/Thumb2SizeReduction.cpp
397 if (!isARMLowRegister(Reg)) 472 assert(isARMLowRegister(Rt)); 473 assert(isARMLowRegister(Rn)); 500 assert(isARMLowRegister(BaseReg)); 546 } else if (!isARMLowRegister(BaseReg) || 641 if (!isARMLowRegister(MI->getOperand(0).getReg())) 752 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) 752 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) 753 || !isARMLowRegister(Reg2)) 777 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) 786 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) 874 if (Entry.LowRegs1 && !isARMLowRegister(Reg))lib/Target/ARM/ThumbRegisterInfo.cpp
111 (isARMLowRegister(DestReg) || Register::isVirtualRegister(DestReg)) && 131 bool isHigh = !isARMLowRegister(DestReg) || 132 (BaseReg != 0 && !isARMLowRegister(BaseReg)); 145 if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg)) 231 } else if (isARMLowRegister(DestReg)) { 241 } else if (isARMLowRegister(BaseReg)) {