reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
10401 DebugLoc dl = MI.getDebugLoc(); 10403 switch (MI.getOpcode()) { 10405 MI.print(errs()); 10411 MachineOperand Def(MI.getOperand(1)); 10412 BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD)) 10414 .add(MI.getOperand(2)) // Rn 10415 .add(MI.getOperand(3)) // PredImm 10416 .add(MI.getOperand(4)) // PredReg 10417 .add(MI.getOperand(0)) // Rt 10418 .cloneMemRefs(MI); 10419 MI.eraseFromParent(); 10427 MI.setDesc(TII->get(ARM::t2STR_PRE)); 10430 MI.setDesc(TII->get(ARM::t2STRB_PRE)); 10433 MI.setDesc(TII->get(ARM::t2STRH_PRE)); 10438 unsigned NewOpc = MI.getOpcode() == ARM::STRi_preidx ? ARM::STR_PRE_IMM 10441 unsigned Offset = MI.getOperand(4).getImm(); 10447 MachineMemOperand *MMO = *MI.memoperands_begin(); 10448 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 10449 .add(MI.getOperand(0)) // Rn_wb 10450 .add(MI.getOperand(1)) // Rt 10451 .add(MI.getOperand(2)) // Rn 10453 .add(MI.getOperand(5)) // pred 10454 .add(MI.getOperand(6)) 10456 MI.eraseFromParent(); 10463 switch (MI.getOpcode()) { 10469 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 10470 for (unsigned i = 0; i < MI.getNumOperands(); ++i) 10471 MIB.add(MI.getOperand(i)); 10472 MI.eraseFromParent(); 10499 if (!MI.killsRegister(ARM::CPSR) && 10500 !checkAndUpdateCPSRKill(MI, thisMBB, TRI)) { 10507 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 10515 .addImm(MI.getOperand(3).getImm()) 10516 .addReg(MI.getOperand(4).getReg()); 10530 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg()) 10531 .addReg(MI.getOperand(1).getReg()) 10533 .addReg(MI.getOperand(2).getReg()) 10536 MI.eraseFromParent(); // The pseudo instruction is gone now. 10543 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end()); 10547 bool RHSisZero = MI.getOpcode() == ARM::BCCZi64; 10549 Register LHS1 = MI.getOperand(1).getReg(); 10550 Register LHS2 = MI.getOperand(2).getReg(); 10560 Register RHS1 = MI.getOperand(3).getReg(); 10561 Register RHS2 = MI.getOperand(4).getReg(); 10571 MachineBasicBlock *destMBB = MI.getOperand(RHSisZero ? 3 : 5).getMBB(); 10573 if (MI.getOperand(0).getImm() == ARMCC::NE) 10585 MI.eraseFromParent(); // The pseudo instruction is gone now. 10597 EmitSjLjDispatchBlock(MI, BB); 10622 Register ABSSrcReg = MI.getOperand(1).getReg(); 10623 Register ABSDstReg = MI.getOperand(0).getReg(); 10624 bool ABSSrcKIll = MI.getOperand(1).isKill(); 10634 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 10672 MI.eraseFromParent(); 10679 return EmitStructByval(MI, BB); 10681 return EmitLowered__chkstk(MI, BB); 10683 return EmitLowered__dbzchk(MI, BB);