reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

lib/Target/AMDGPU/SIRegisterInfo.h

  204   bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;

References

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

  592     if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
  614     if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
  727   if (!TRI->isVGPR(MRI, Def.getReg()))
  835     if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
 1220         if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
 1377     if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg()))

lib/Target/AMDGPU/SIFoldOperands.cpp

  411             !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg()))
  764           TRI->isVGPR(*MRI, UseMI->getOperand(1).getReg()))
  766       else if (TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) &&

lib/Target/AMDGPU/SIInsertSkips.cpp

  253     if (TRI->isVGPR(MBB.getParent()->getRegInfo(),

lib/Target/AMDGPU/SIInsertWaitcnts.cpp

  478   if (TRI->isVGPR(MRIA, Op.getReg())) {
  509     assert(TRI->isVGPR(*MRI, Opnd.getReg()));
  573           if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) {
  621               TRI->isVGPR(MRIA, DefMO.getReg())) {
  629         if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) {
  993           if (TRI->isVGPR(MRIA, Op.getReg())) {
 1029           if (TRI->isVGPR(MRIA, Def.getReg())) {

lib/Target/AMDGPU/SIInstrInfo.cpp

 2333     bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
 3006         if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
 3015         if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
 3026   if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
 4036     if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
 4042     if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
 4068       RI.isVGPR(MRI, Src1.getReg())) {

lib/Target/AMDGPU/SIInstrInfo.h

  683       return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

 1178     if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg())))

lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

   95   if (!TRI->isVGPR(*MRI, Reg))

lib/Target/AMDGPU/SIRegisterInfo.cpp

  565   unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32

lib/Target/AMDGPU/SIRegisterInfo.h

  207     return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  472   if (!TRI.isVGPR(MRI, X))
  488     if (!TRI.isVGPR(MRI, Y) || MovT.getParent() != MovY.getParent())

lib/Target/AMDGPU/SIWholeQuadMode.cpp

  860     if (TRI->isVGPR(*MRI, Reg)) {