reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
132 if (TII->hasUnwantedEffectsWhenEXECEmpty(*I)) 136 if (TII->isSMRD(*I) || TII->isVMEM(*I) || TII->isFLAT(*I) || 136 if (TII->isSMRD(*I) || TII->isVMEM(*I) || TII->isFLAT(*I) || 136 if (TII->isSMRD(*I) || TII->isVMEM(*I) || TII->isFLAT(*I) || 162 BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 168 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE)) 179 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0); 256 BuildMI(MBB, &MI, DL, TII->get(Opcode)) 260 auto I = BuildMI(MBB, &MI, DL, TII->get(Opcode)); 287 BuildMI(MBB, &MI, DL, TII->get(ST.isWave32() ? AMDGPU::S_MOV_B32 296 BuildMI(MBB, &MI, DL, TII->get(Opcode), Exec) 331 BuildMI(SrcMBB, InsPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) 374 TII->commuteInstruction(*A); 417 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); 419 MI.setDesc(TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ 431 TII = ST.getInstrInfo(); 432 TRI = &TII->getRegisterInfo(); 520 BuildMI(*BI, I, MI.getDebugLoc(), TII->get(AMDGPU::S_BRANCH))