reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Overrides

include/llvm/CodeGen/TargetSubtargetInfo.h

  123   virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }

References

lib/Target/AMDGPU/AMDGPUCallLowering.cpp

  328     const SIRegisterInfo *TRI = ST.getRegisterInfo();
  444   const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
  569   const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  556         = static_cast<const GCNSubtarget *>(Subtarget)->getRegisterInfo();
  574     return Subtarget->getRegisterInfo()->getRegClass(RegClass);
  579         Subtarget->getRegisterInfo()->getRegClass(RCID);
  583     return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
 1112   const SIRegisterInfo *TRI = ST->getRegisterInfo();
 2047   const SIRegisterInfo *TRI = ST->getRegisterInfo();
 2637     static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

   52       TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

  346                                     *STI.getRegisterInfo());

lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

 2877   TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

   91       TRI(Subtarget.getRegisterInfo()),

lib/Target/AMDGPU/AMDGPUSubtarget.h

 1176     return getRegisterInfo()->getBoolRC();

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

  446   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  604   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  722   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  786   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  825   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  914   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  965   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 1037   const SIRegisterInfo *TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/GCNNSAReassign.cpp

  229   TRI = ST->getRegisterInfo();

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  733   TRI = ST->getRegisterInfo();

lib/Target/AMDGPU/SIAddIMGInit.cpp

   66   const SIRegisterInfo *RI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  591   TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIFixVGPRCopies.cpp

   50   const SIRegisterInfo *TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIFixupVectorISel.cpp

  226   const SIRegisterInfo *TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  313   TRI = ST->getRegisterInfo();

lib/Target/AMDGPU/SIFrameLowering.cpp

  885         LiveRegs.init(*ST.getRegisterInfo());
  945   const SIRegisterInfo *RI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
  957   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  995   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 1069   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 1150     MF.getSubtarget<GCNSubtarget>().getRegisterInfo()->needsStackRealignment(MF) ||

lib/Target/AMDGPU/SIISelLowering.cpp

  161   computeRegisterProperties(Subtarget->getRegisterInfo());
 1985   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
 2021   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
 2294     const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
 2342     const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
 2444   const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
 2595   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
 2897     const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
 2946   auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
 3001        Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
 3180   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 3280   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 3602     const SIRegisterInfo *TRI = ST.getRegisterInfo();
 3751     const SIRegisterInfo *TRI = ST.getRegisterInfo();
 3841       const SIRegisterInfo *TRI = ST.getRegisterInfo();
 4551   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
10401       const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
10678   const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
10939   const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
11017       const SIRegisterInfo *SIRI = Subtarget->getRegisterInfo();
11020           MF.getDataLayout(), Subtarget->getRegisterInfo(), CS);

lib/Target/AMDGPU/SIInstrInfo.cpp

 4324   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 4407   const SIRegisterInfo *TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

  270   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  348   const SIRegisterInfo *TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

  272   const SIRegisterInfo *TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

  192   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  298   TRI = ST.getRegisterInfo();

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

 1211   TRI = ST.getRegisterInfo();