reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
448 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp97 return Reg == TRI.getVCC(); 104 return RC->hasSuperClassEq(TRI.getBoolRC()) && 125 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); 133 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) 141 MRI->setRegClass(SrcReg, TRI.getConstrainedRegClassForOperand(Src, *MRI)); 147 TRI.getConstrainedRegClassForOperand(Dst, *MRI); 159 TRI.getConstrainedRegClassForOperand(Src, *MRI); 172 TRI.getConstrainedRegClassForOperand(MO, *MRI); 203 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI); 224 unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx); 267 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); 269 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 271 const TargetRegisterClass *RC = TRI.getBoolRC(); 293 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 304 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); 305 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 317 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); 325 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 330 Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass()); 338 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); 364 const TargetRegisterClass *CarryRC = TRI.getWaveMaskRegClass(); 378 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI)) 413 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 443 unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32); 451 TRI.getConstrainedRegClassForOperand(MO, *MRI); 471 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); 474 TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI); 478 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); 487 = TRI.getConstrainedRegClassForOperand(Src, *MRI); 513 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); 516 TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank, *MRI); 525 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); 532 TRI.getConstrainedRegClassForOperand(Dst, *MRI); 550 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); 575 unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32, InsSize / 32); 579 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); 581 TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI); 585 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); 586 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); 588 TRI.getRegClassForSizeOnBank(DstSize, *Src0Bank, *MRI); 590 TRI.getRegClassForSizeOnBank(InsSize, *Src1Bank, *MRI); 594 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg); 633 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); 721 unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI); 736 constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) && 751 *TRI.getBoolRC(), *MRI); 752 bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); 1029 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); 1050 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); 1067 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); 1080 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); 1097 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); 1111 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); 1116 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) | 1117 constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI); 1134 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); 1173 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 1174 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); 1182 = TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB, *MRI); 1184 = TRI.getRegClassForSizeOnBank(DstSize, *DstRB, *MRI); 1193 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx); 1232 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); 1271 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); 1288 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); 1298 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); 1391 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) 1418 const TargetRegisterClass *RC = TRI.getRegClassForReg(*MRI, DstReg); 1419 IsSgpr = TRI.isSGPRClass(RC); 1420 Size = TRI.getRegSizeInBits(*RC); 1430 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1464 TRI.getConstrainedRegClassForOperand(ResInst->getOperand(0), *MRI); 1497 const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI); 1582 CondPhysReg = TRI.getVCC(); 1584 ConstrainRC = TRI.getBoolRC(); 1602 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 1621 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 1622 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); 1631 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB, 1633 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB,