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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 448 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 115 I.setDesc(TII.get(TargetOpcode::COPY));
136 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
210 I.setDesc(TII.get(TargetOpcode::PHI));
226 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
274 I.setDesc(TII.get(InstOpc));
292 I.setDesc(TII.get(InstOpc));
293 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
313 BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
317 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
322 I.setDesc(TII.get(Opc));
325 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
332 = BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
338 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
357 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
360 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
366 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_I32_e64), DstLo)
371 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi)
378 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI))
382 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
410 I.setDesc(TII.get(NewOpc));
413 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
419 BuildMI(*BB, &I, DL, TII.get(NewOpc), Dst0Reg)
422 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), Dst1Reg)
445 MachineInstr *Copy = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY),
480 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::REG_SEQUENCE), DstReg);
528 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
553 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
604 BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG), DstReg)
621 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::SI_IF_BREAK))
730 MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode))
733 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
736 constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) &&
746 MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
752 bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
965 TII.getAddNoCarry(B.getMBB(), B.getInsertPt(), B.getDebugLoc(), NewBaseReg)
1029 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1043 MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(),
1050 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
1062 BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef);
1063 MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM,
1067 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
1073 TII.get(AMDGPU::SI_END_CF))
1104 MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1112 MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
1116 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) |
1117 constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI);
1127 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1134 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
1206 I.setDesc(TII.get(TargetOpcode::COPY));
1246 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), TmpReg)
1248 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1252 BuildMI(MBB, I, DL, TII.get(Opcode), DstReg)
1264 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1271 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
1284 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg)
1288 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
1293 BuildMI(MBB, I, DL, TII.get(BFE), DstReg)
1298 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
1308 BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg)
1322 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
1323 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg)
1329 BuildMI(MBB, I, DL, TII.get(BFE64), DstReg)
1339 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg)
1343 BuildMI(MBB, I, DL, TII.get(BFE32), DstReg)
1382 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1387 auto MIB = BuildMI(*MBB, I, DL, TII.get(NewOpc), DstReg)
1391 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
1428 I.setDesc(TII.get(Opcode));
1430 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1438 if (IsSgpr && TII.isInlineConstant(Imm)) {
1439 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B64), DstReg)
1447 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
1450 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
1453 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
1546 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1591 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CondPhysReg)
1593 BuildMI(*BB, &I, DL, TII.get(BrOpcode))
1604 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32));
1641 BuildMI(*BB, &I, DL, TII.get(MovOpc), ImmReg)
1645 BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg)
1656 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg)
1658 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
1661 BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskLo)
1664 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
1761 I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));
1941 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
1973 if (!TII.isLegalFLATOffset(Offset.getValue(), AddrSpace, Signed))
2013 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::V_MOV_B32_e32),