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reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc
  448   if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  128       return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
  133       if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))
  148     if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
  160       if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
  175     RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
  211   return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI);
  267   unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
  269   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
  285     return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
  293     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
  304   unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
  305   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
  317       return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
  325       return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
  338     return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
  378     if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI))
  389   if (!RBI.constrainGenericRegister(DstReg, RC, *MRI))
  413     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
  428   if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, MRI) ||
  429       !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, MRI) ||
  430       !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, MRI))
  454     RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
  471   const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
  488     if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))
  492   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
  513   const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
  517   if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
  533     if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
  552       (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) {
  579   const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
  585   const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI);
  586   const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI);
  598   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
  599       !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) ||
  600       !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI))
  721   unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI);
  736         constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) &&
  737         RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
  750   RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
  752   bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
 1029   return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
 1050     return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
 1067     return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
 1097   unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
 1116     bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) |
 1117                constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI);
 1134   bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
 1173   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
 1174   const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
 1200   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
 1201       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) {
 1232   const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
 1256     return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI);
 1271     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
 1288       return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
 1298     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
 1302     if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, *MRI))
 1311       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);
 1334       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI);
 1349     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);
 1391   if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
 1430     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 1467   return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI);
 1497     const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
 1602   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
 1608   return RBI.constrainGenericRegister(
 1621   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
 1622   const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
 1635   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
 1636       !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))