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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1029 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/AArch64/AArch64InstructionSelector.cpp 983 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI);
1003 .constrainAllUses(TII, TRI, RBI);
1034 constrainSelectedInstRegOperands(*UShl, TII, TRI, RBI);
1076 constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI);
1078 constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI);
1102 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1110 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1127 constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);
1144 constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
1230 return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
1267 if (RBI.getRegBank(StoreSrcReg, MRI, TRI) ==
1268 RBI.getRegBank(DefDstReg, MRI, TRI))
1330 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1360 return selectCopy(I, TII, MRI, TRI, RBI);
1422 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
1428 constrainSelectedInstRegOperands(*CMP.getInstr(), TII, TRI, RBI);
1435 return constrainSelectedInstRegOperands(*Bcc.getInstr(), TII, TRI, RBI);
1441 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1481 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1497 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1576 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1595 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
1596 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1625 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1636 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1657 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1671 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1686 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1713 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1737 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1746 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
1755 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
1814 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1818 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1824 if (unsupportedBinOp(I, RBI, MRI, TRI))
1828 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1847 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1866 if (unsupportedBinOp(I, RBI, MRI, TRI))
1872 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1883 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1915 constrainSelectedInstRegOperands(*AddsMI, TII, TRI, RBI);
1925 constrainSelectedInstRegOperands(*CsetMI, TII, TRI, RBI);
1939 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1949 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1950 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
1995 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2017 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
2024 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);
2054 return selectCopy(I, TII, MRI, TRI, RBI);
2071 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==
2087 RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID) {
2091 return selectCopy(I, TII, MRI, TRI, RBI);
2122 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
2138 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2147 return selectCopy(I, TII, MRI, TRI, RBI);
2155 return selectCopy(I, TII, MRI, TRI, RBI);
2184 constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI);
2185 constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI);
2263 constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
2264 constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
2266 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
2267 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
2283 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2304 return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
2366 return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
2391 .addRegMask(TRI.getTLSCallPreservedMask());
2452 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2507 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2651 const RegisterBank &VecRB = *RBI.getRegBank(SrcReg, MRI, TRI);
2668 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
2673 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
2692 constrainSelectedInstRegOperands(*Undef, TII, TRI, RBI);
2693 constrainSelectedInstRegOperands(*Ins, TII, TRI, RBI);
2715 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
2737 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
2738 constrainSelectedInstRegOperands(*Ins2MI, TII, TRI, RBI);
2772 constrainSelectedInstRegOperands(SubRegMI, TII, TRI, RBI);
2773 constrainSelectedInstRegOperands(SubRegMI2, TII, TRI, RBI);
2774 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI);
2823 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI);
2857 constrainSelectedInstRegOperands(*LaneCopyMI, TII, TRI, RBI);
2881 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
2894 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2922 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);
2940 if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
2942 RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
3005 constrainSelectedInstRegOperands(ImpDefMI, TII, TRI, RBI);
3006 constrainSelectedInstRegOperands(InsMI, TII, TRI, RBI);
3020 constrainSelectedInstRegOperands(*FirstCopy, TII, TRI, RBI);
3030 constrainSelectedInstRegOperands(CopyInst, TII, TRI, RBI);
3104 constrainSelectedInstRegOperands(*Adrp, TII, TRI, RBI);
3105 constrainSelectedInstRegOperands(*LoadMI, TII, TRI, RBI);
3165 constrainSelectedInstRegOperands(*AddMI, TII, TRI, RBI);
3191 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
3219 constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
3267 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
3301 const RegisterBank &FPRBank = *RBI.getRegBank(Op1, MRI, TRI);
3327 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
3360 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
3374 constrainSelectedInstRegOperands(*I, TII, TRI, RBI);
3713 constrainSelectedInstRegOperands(*TBL1, TII, TRI, RBI);
3736 constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
3737 constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);
3769 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
3799 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
3823 getMinClassForRegBank(*RBI.getRegBank(DemoteVec, MRI, TRI), VecSize);
3829 if (!getSubRegForClass(RC, TRI, SubReg))
3842 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
3859 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
3888 getMinClassForRegBank(*RBI.getRegBank(DstVec, MRI, TRI), DstSize);
3897 if (!getSubRegForClass(RC, TRI, SubReg))
3918 constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI);
3983 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
3992 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID)
3997 constrainSelectedInstRegOperands(*SHA1Inst, TII, TRI, RBI);
4563 selectCopy(*Copy, TII, MRI, TRI, RBI);