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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1029 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/AArch64/AArch64InstructionSelector.cpp 1000 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CBOpc))
1003 .constrainAllUses(TII, TRI, RBI);
1034 constrainSelectedInstRegOperands(*UShl, TII, TRI, RBI);
1076 constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI);
1078 constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI);
1096 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::ADDXri))
1102 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1104 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::STRXui))
1110 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1127 constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);
1144 constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
1230 return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
1308 I.setDesc(TII.get(TargetOpcode::COPY));
1330 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1354 I.setDesc(TII.get(TargetOpcode::PHI));
1360 return selectCopy(I, TII, MRI, TRI, RBI);
1416 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
1422 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
1424 auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
1428 constrainSelectedInstRegOperands(*CMP.getInstr(), TII, TRI, RBI);
1430 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::Bcc))
1435 return constrainSelectedInstRegOperands(*Bcc.getInstr(), TII, TRI, RBI);
1440 I.setDesc(TII.get(AArch64::BR));
1441 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1480 I.setDesc(TII.get(Opc));
1481 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1575 I.setDesc(TII.get(MovOpc));
1576 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1618 I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri));
1625 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1636 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1648 I.setDesc(TII.get(DstSize == 64 ? AArch64::BFMXri : AArch64::BFMWri));
1657 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1662 TII.get(AArch64::SUBREG_TO_REG))
1671 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1680 I.setDesc(TII.get(AArch64::ADDXri));
1686 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1696 I.setDesc(TII.get(AArch64::LOADgot));
1704 I.setDesc(TII.get(AArch64::ADR));
1707 I.setDesc(TII.get(AArch64::MOVaddr));
1713 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1736 I.setDesc(TII.get(AArch64::LDARB));
1737 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1762 I.setDesc(TII.get(NewOpc));
1814 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1818 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1843 I.setDesc(TII.get(NewOpc));
1847 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1878 I.setDesc(TII.get(NewOpc));
1883 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1915 constrainSelectedInstRegOperands(*AddsMI, TII, TRI, RBI);
1925 constrainSelectedInstRegOperands(*CsetMI, TII, TRI, RBI);
1936 I.setDesc(TII.get(AArch64::ANDXri));
1939 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1990 I.setDesc(TII.get(TargetOpcode::COPY));
1994 I.setDesc(TII.get(AArch64::XTNv4i16));
1995 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2047 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
2054 return selectCopy(I, TII, MRI, TRI, RBI);
2091 return selectCopy(I, TII, MRI, TRI, RBI);
2098 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(Opcode)
2122 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
2137 I.setDesc(TII.get(NewOpc));
2138 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2147 return selectCopy(I, TII, MRI, TRI, RBI);
2155 return selectCopy(I, TII, MRI, TRI, RBI);
2173 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
2178 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc))
2184 constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI);
2185 constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI);
2229 auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
2244 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
2253 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
2259 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
2263 constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
2264 constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
2266 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
2267 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
2280 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
2295 I.setDesc(TII.get(AArch64::MOVaddrBA));
2296 auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA),
2304 return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
2366 return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
2451 I.setDesc(TII.get(Opc));
2452 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2506 I.setDesc(TII.get(Opc));
2507 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2668 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
2673 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
2692 constrainSelectedInstRegOperands(*Undef, TII, TRI, RBI);
2693 constrainSelectedInstRegOperands(*Ins, TII, TRI, RBI);
2737 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
2738 constrainSelectedInstRegOperands(*Ins2MI, TII, TRI, RBI);
2752 TII.get(TargetOpcode::SUBREG_TO_REG))
2760 TII.get(TargetOpcode::SUBREG_TO_REG))
2766 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri))
2772 constrainSelectedInstRegOperands(SubRegMI, TII, TRI, RBI);
2773 constrainSelectedInstRegOperands(SubRegMI2, TII, TRI, RBI);
2774 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI);
2857 constrainSelectedInstRegOperands(*LaneCopyMI, TII, TRI, RBI);
2993 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
3000 TII.get(TargetOpcode::INSERT_SUBREG), InsertReg)
3005 constrainSelectedInstRegOperands(ImpDefMI, TII, TRI, RBI);
3006 constrainSelectedInstRegOperands(InsMI, TII, TRI, RBI);
3020 constrainSelectedInstRegOperands(*FirstCopy, TII, TRI, RBI);
3027 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CopyOpc), CopyTo)
3030 constrainSelectedInstRegOperands(CopyInst, TII, TRI, RBI);
3104 constrainSelectedInstRegOperands(*Adrp, TII, TRI, RBI);
3105 constrainSelectedInstRegOperands(*LoadMI, TII, TRI, RBI);
3165 constrainSelectedInstRegOperands(*AddMI, TII, TRI, RBI);
3191 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
3219 constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
3267 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
3327 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
3359 I.setDesc(TII.get(MovOpc));
3360 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
3374 constrainSelectedInstRegOperands(*I, TII, TRI, RBI);
3461 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
3470 constrainSelectedInstRegOperands(*CSel, TII, TRI, RBI);
3634 constrainSelectedInstRegOperands(*Dup, TII, TRI, RBI);
3713 constrainSelectedInstRegOperands(*TBL1, TII, TRI, RBI);
3736 constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
3737 constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);
3769 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
3842 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
3918 constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI);
3997 constrainSelectedInstRegOperands(*SHA1Inst, TII, TRI, RBI);
4563 selectCopy(*Copy, TII, MRI, TRI, RBI);