reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1334 const LLT DefTy = MRI.getType(DefReg); 1337 MRI.getRegClassOrRegBank(DefReg); 1356 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); 1360 return selectCopy(I, TII, MRI, TRI, RBI); 1389 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{}; 1412 if (ProduceNonFlagSettingCondBr && selectCompareBranch(I, MF, MRI)) 1445 return selectBrJT(I, MRI); 1450 LLT DstTy = MRI.getType(DstReg); 1495 const LLT DefTy = MRI.getType(DefReg); 1497 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); 1548 if (emitFMovForFConstant(I, MRI)) 1552 const Register DefGPRReg = MRI.createVirtualRegister(&GPRRC); 1558 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) { 1582 LLT SrcTy = MRI.getType(SrcReg); 1583 LLT DstTy = MRI.getType(DstReg); 1595 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); 1596 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); 1628 DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); 1633 AArch64::GPR32RegClass, MRI); 1640 LLT SrcTy = MRI.getType(I.getOperand(2).getReg()); 1641 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); 1650 unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); 1660 Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); 1668 AArch64::GPR32RegClass, MRI); 1692 return selectTLSGlobalValue(I, MRI); 1722 LLT PtrTy = MRI.getType(I.getOperand(1).getReg()); 1746 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); 1750 assert(MRI.getType(PtrReg).isPointer() && 1755 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); 1765 auto *PtrMI = MRI.getVRegDef(PtrReg); 1769 if (auto COff = getConstantVRegVal(PtrMI->getOperand(2).getReg(), MRI)) { 1776 PtrMI = MRI.getVRegDef(Ptr2Reg); 1790 if (auto CVal = getConstantVRegVal(ValReg, MRI)) { 1801 if (MRI.getType(ValReg).getSizeInBits() != 64) 1805 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); 1816 MRI); 1824 if (unsupportedBinOp(I, RBI, MRI, TRI)) 1828 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); 1855 if (MRI.getType(I.getOperand(0).getReg()).isVector()) 1856 return selectVectorASHR(I, MRI); 1860 MRI.getType(I.getOperand(0).getReg()).isVector()) 1861 return selectVectorSHL(I, MRI); 1866 if (unsupportedBinOp(I, RBI, MRI, TRI)) 1872 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); 1943 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); 1944 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); 1949 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); 1950 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); 1969 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || 1970 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { 2017 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI); 2024 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI); 2031 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); 2046 Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass); 2054 return selectCopy(I, TII, MRI, TRI, RBI); 2063 const LLT DstTy = MRI.getType(DefReg); 2064 const LLT SrcTy = MRI.getType(SrcReg); 2071 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() == 2085 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); 2087 RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID) { 2091 return selectCopy(I, TII, MRI, TRI, RBI); 2097 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) { 2131 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()), 2132 SrcTy = MRI.getType(I.getOperand(1).getReg()); 2147 return selectCopy(I, TII, MRI, TRI, RBI); 2155 return selectCopy(I, TII, MRI, TRI, RBI); 2158 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) { 2171 Register CSelOpc = selectSelectOpc(I, MRI, RBI); 2192 return selectVectorICmp(I, MRI); 2217 unsigned CmpOpc = selectFCMPOpc(I, MRI); 2241 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); 2251 Register Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); 2273 return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI) 2274 : selectVaStartAAPCS(I, MF, MRI); 2276 return selectIntrinsic(I, MRI); 2278 return selectIntrinsicWithSideEffects(I, MRI); 2281 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); 2283 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); 2286 RBI.constrainGenericRegister(DstReg, *DstRC, MRI); 2308 return selectIntrinsicTrunc(I, MRI); 2310 return selectIntrinsicRound(I, MRI); 2312 return selectBuildVector(I, MRI); 2314 return selectMergeValues(I, MRI); 2316 return selectUnmergeValues(I, MRI); 2318 return selectShuffleVector(I, MRI); 2320 return selectExtractElt(I, MRI); 2322 return selectInsertElt(I, MRI); 2324 return selectConcatVectors(I, MRI); 2326 return selectJumpTable(I, MRI);