reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2711 assert(I.getOpcode() == TargetOpcode::G_MERGE_VALUES && "unexpected opcode"); 2712 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); 2713 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); 2715 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI); 2717 if (I.getNumOperands() != 3) 2724 MachineIRBuilder MIB(I); 2725 Register DstReg = I.getOperand(0).getReg(); 2726 Register Src1Reg = I.getOperand(1).getReg(); 2727 Register Src2Reg = I.getOperand(2).getReg(); 2739 I.eraseFromParent(); 2751 MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 2751 MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 2751 MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 2755 .addUse(I.getOperand(1).getReg()) 2759 MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 2759 MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 2759 MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 2763 .addUse(I.getOperand(2).getReg()) 2766 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri)) 2766 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri)) 2766 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri)) 2767 .addDef(I.getOperand(0).getReg()) 2775 I.eraseFromParent();