reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1317 assert(I.getParent() && "Instruction should be in a basic block!"); 1318 assert(I.getParent()->getParent() && "Instruction should be in a function!"); 1320 MachineBasicBlock &MBB = *I.getParent(); 1324 unsigned Opcode = I.getOpcode(); 1330 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1333 const Register DefReg = I.getOperand(0).getReg(); 1354 I.setDesc(TII.get(TargetOpcode::PHI)); 1359 if (I.isCopy()) 1360 return selectCopy(I, TII, MRI, TRI, RBI); 1366 if (I.getNumOperands() != I.getNumExplicitOperands()) { 1366 if (I.getNumOperands() != I.getNumExplicitOperands()) { 1375 preISelLower(I); 1382 if (earlySelect(I)) 1385 if (selectImpl(I, *CoverageInfo)) 1389 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{}; 1389 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{}; 1391 MachineIRBuilder MIB(I); 1404 const Register CondReg = I.getOperand(0).getReg(); 1405 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); 1412 if (ProduceNonFlagSettingCondBr && selectCompareBranch(I, MF, MRI)) 1416 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW)) 1416 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW)) 1421 I.eraseFromParent(); 1424 auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) 1424 auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) 1430 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::Bcc)) 1430 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::Bcc)) 1434 I.eraseFromParent(); 1440 I.setDesc(TII.get(AArch64::BR)); 1441 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1445 return selectBrJT(I, MRI); 1449 Register DstReg = I.getOperand(0).getReg(); 1480 I.setDesc(TII.get(Opc)); 1481 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1494 const Register DefReg = I.getOperand(0).getReg(); 1517 if (I.getOperand(1).getFPImm()->getValueAPF().isExactlyValue(0.0)) 1548 if (emitFMovForFConstant(I, MRI)) 1553 MachineOperand &RegOp = I.getOperand(0); 1555 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator())); 1563 MachineOperand &ImmOp = I.getOperand(1); 1567 } else if (I.getOperand(1).isCImm()) { 1568 uint64_t Val = I.getOperand(1).getCImm()->getZExtValue(); 1569 I.getOperand(1).ChangeToImmediate(Val); 1570 } else if (I.getOperand(1).isImm()) { 1571 uint64_t Val = I.getOperand(1).getImm(); 1572 I.getOperand(1).ChangeToImmediate(Val); 1575 I.setDesc(TII.get(MovOpc)); 1576 constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1580 Register DstReg = I.getOperand(0).getReg(); 1581 Register SrcReg = I.getOperand(1).getReg(); 1605 unsigned Offset = I.getOperand(2).getImm(); 1609 MachineIRBuilder MIB(I); 1614 I.eraseFromParent(); 1618 I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri)); 1619 MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() + 1619 MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() + 1625 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1629 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator())); 1630 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) 1632 RBI.constrainGenericRegister(I.getOperand(0).getReg(), 1634 I.getOperand(0).setReg(DstReg); 1636 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1640 LLT SrcTy = MRI.getType(I.getOperand(2).getReg()); 1641 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); 1648 I.setDesc(TII.get(DstSize == 64 ? AArch64::BFMXri : AArch64::BFMWri)); 1649 unsigned LSB = I.getOperand(3).getImm(); 1650 unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); 1651 I.getOperand(3).setImm((DstSize - LSB) % DstSize); 1652 MachineInstrBuilder(MF, I).addImm(Width - 1); 1657 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1661 BuildMI(MBB, I.getIterator(), I.getDebugLoc(), 1661 BuildMI(MBB, I.getIterator(), I.getDebugLoc(), 1665 .addUse(I.getOperand(2).getReg()) 1667 RBI.constrainGenericRegister(I.getOperand(2).getReg(), 1669 I.getOperand(2).setReg(SrcReg); 1671 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1680 I.setDesc(TII.get(AArch64::ADDXri)); 1683 I.addOperand(MachineOperand::CreateImm(0)); 1684 I.addOperand(MachineOperand::CreateImm(0)); 1686 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1690 auto GV = I.getOperand(1).getGlobal(); 1692 return selectTLSGlobalValue(I, MRI); 1696 I.setDesc(TII.get(AArch64::LOADgot)); 1697 I.getOperand(1).setTargetFlags(OpFlags); 1700 materializeLargeCMVal(I, GV, OpFlags); 1701 I.eraseFromParent(); 1704 I.setDesc(TII.get(AArch64::ADR)); 1705 I.getOperand(1).setTargetFlags(OpFlags); 1707 I.setDesc(TII.get(AArch64::MOVaddr)); 1708 I.getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_PAGE); 1709 MachineInstrBuilder MIB(MF, I); 1710 MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(), 1713 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1719 bool IsZExtLoad = I.getOpcode() == TargetOpcode::G_ZEXTLOAD; 1720 MachineIRBuilder MIB(I); 1722 LLT PtrTy = MRI.getType(I.getOperand(1).getReg()); 1730 auto &MemOp = **I.memoperands_begin(); 1736 I.setDesc(TII.get(AArch64::LDARB)); 1737 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1744 const Register PtrReg = I.getOperand(1).getReg(); 1754 const Register ValReg = I.getOperand(0).getReg(); 1758 selectLoadStoreUIOp(I.getOpcode(), RB.getID(), MemSizeInBits); 1759 if (NewOpc == I.getOpcode()) 1762 I.setDesc(TII.get(NewOpc)); 1775 I.getOperand(1).setReg(Ptr2Reg); 1785 I.getOperand(1).ChangeToFrameIndex(PtrMI->getOperand(1).getIndex()); 1787 I.addOperand(MachineOperand::CreateImm(Offset)); 1792 if (I.getOpcode() == AArch64::STRWui) 1793 I.getOperand(0).setReg(AArch64::WZR); 1794 else if (I.getOpcode() == AArch64::STRXui) 1795 I.getOperand(0).setReg(AArch64::XZR); 1806 Register DstReg = I.getOperand(0).getReg(); 1807 I.getOperand(0).setReg(LdReg); 1809 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator())); 1814 constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1818 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1824 if (unsupportedBinOp(I, RBI, MRI, TRI)) 1827 const Register DefReg = I.getOperand(0).getReg(); 1841 unsigned NewOpc = I.getOpcode() == TargetOpcode::G_SMULH ? AArch64::SMULHrr 1843 I.setDesc(TII.get(NewOpc)); 1847 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1855 if (MRI.getType(I.getOperand(0).getReg()).isVector()) 1856 return selectVectorASHR(I, MRI); 1860 MRI.getType(I.getOperand(0).getReg()).isVector()) 1861 return selectVectorSHL(I, MRI); 1866 if (unsupportedBinOp(I, RBI, MRI, TRI)) 1871 const Register DefReg = I.getOperand(0).getReg(); 1874 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize); 1875 if (NewOpc == I.getOpcode()) 1878 I.setDesc(TII.get(NewOpc)); 1883 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1887 MachineIRBuilder MIRBuilder(I); 1888 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2), 1888 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2), 1888 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2), 1890 I.eraseFromParent(); 1911 MachineIRBuilder MIRBuilder(I); 1913 AddsOpc, {I.getOperand(0).getReg()}, 1914 {I.getOperand(2).getReg(), I.getOperand(3).getReg()}); 1914 {I.getOperand(2).getReg(), I.getOperand(3).getReg()}); 1922 .buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()}, 1926 I.eraseFromParent(); 1931 uint64_t Align = I.getOperand(2).getImm(); 1936 I.setDesc(TII.get(AArch64::ANDXri)); 1937 I.getOperand(2).setImm(AArch64_AM::encodeLogicalImmediate(Mask, 64)); 1939 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1943 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); 1944 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); 1946 const Register DstReg = I.getOperand(0).getReg(); 1947 const Register SrcReg = I.getOperand(1).getReg(); 1983 I.getOperand(1).setSubReg(AArch64::sub_32); 1990 I.setDesc(TII.get(TargetOpcode::COPY)); 1994 I.setDesc(TII.get(AArch64::XTNv4i16)); 1995 constrainSelectedInstRegOperands(I, TII, TRI, RBI); 2000 MachineIRBuilder MIB(I); 2005 I.eraseFromParent(); 2014 const Register DstReg = I.getOperand(0).getReg(); 2015 const Register SrcReg = I.getOperand(1).getReg(); 2047 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) 2047 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) 2052 I.getOperand(1).setReg(ExtSrc); 2054 return selectCopy(I, TII, MRI, TRI, RBI); 2059 unsigned Opcode = I.getOpcode(); 2061 const Register DefReg = I.getOperand(0).getReg(); 2062 const Register SrcReg = I.getOperand(1).getReg(); 2075 MachineIRBuilder MIB(I); 2091 return selectCopy(I, TII, MRI, TRI, RBI); 2123 I.eraseFromParent(); 2131 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()), 2132 SrcTy = MRI.getType(I.getOperand(1).getReg()); 2137 I.setDesc(TII.get(NewOpc)); 2138 constrainSelectedInstRegOperands(I, TII, TRI, RBI); 2147 return selectCopy(I, TII, MRI, TRI, RBI); 2155 return selectCopy(I, TII, MRI, TRI, RBI); 2158 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) { 2164 const Register CondReg = I.getOperand(1).getReg(); 2165 const Register TReg = I.getOperand(2).getReg(); 2166 const Register FReg = I.getOperand(3).getReg(); 2168 if (tryOptSelect(I)) 2171 Register CSelOpc = selectSelectOpc(I, MRI, RBI); 2173 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) 2173 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) 2178 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc)) 2178 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc)) 2179 .addDef(I.getOperand(0).getReg()) 2187 I.eraseFromParent(); 2192 return selectVectorICmp(I, MRI); 2200 MachineIRBuilder MIRBuilder(I); 2201 if (!emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1), 2201 if (!emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1), 2201 if (!emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1), 2204 emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(), 2204 emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(), 2206 I.eraseFromParent(); 2217 unsigned CmpOpc = selectFCMPOpc(I, MRI); 2225 (CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2); 2229 auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc)) 2229 auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc)) 2230 .addUse(I.getOperand(2).getReg()); 2236 CmpMI = CmpMI.addUse(I.getOperand(3).getReg()); 2238 const Register DefReg = I.getOperand(0).getReg(); 2244 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) 2244 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) 2253 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) 2253 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) 2259 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr)) 2259 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr)) 2269 I.eraseFromParent(); 2273 return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI) 2274 : selectVaStartAAPCS(I, MF, MRI); 2276 return selectIntrinsic(I, MRI); 2278 return selectIntrinsicWithSideEffects(I, MRI); 2280 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); 2281 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); 2282 const Register DstReg = I.getOperand(0).getReg(); 2291 materializeLargeCMVal(I, I.getOperand(1).getBlockAddress(), 0); 2291 materializeLargeCMVal(I, I.getOperand(1).getBlockAddress(), 0); 2292 I.eraseFromParent(); 2295 I.setDesc(TII.get(AArch64::MOVaddrBA)); 2296 auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA), 2296 auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA), 2297 I.getOperand(0).getReg()) 2298 .addBlockAddress(I.getOperand(1).getBlockAddress(), 2301 I.getOperand(1).getBlockAddress(), /* Offset */ 0, 2303 I.eraseFromParent(); 2308 return selectIntrinsicTrunc(I, MRI); 2310 return selectIntrinsicRound(I, MRI); 2312 return selectBuildVector(I, MRI); 2314 return selectMergeValues(I, MRI); 2316 return selectUnmergeValues(I, MRI); 2318 return selectShuffleVector(I, MRI); 2320 return selectExtractElt(I, MRI); 2322 return selectInsertElt(I, MRI); 2324 return selectConcatVectors(I, MRI); 2326 return selectJumpTable(I, MRI);