reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/TargetRegisterInfo.h
  312     getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;

References

lib/CodeGen/AggressiveAntiDepBreaker.cpp
  630     TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
lib/CodeGen/AsmPrinter/DwarfExpression.cpp
  136   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
  104   const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
lib/CodeGen/MachineCopyPropagation.cpp
  350       TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg());
lib/CodeGen/PrologEpilogInserter.cpp
  418       const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
  551         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
  578         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  157   SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
  574           TRI->getMinimalPhysRegClass(Reg, VT);
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 1558       TRI->getMinimalPhysRegClass(Reg, VT);
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  134         TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
lib/CodeGen/StackMaps.cpp
  153     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
  249   unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg));
lib/CodeGen/TargetRegisterInfo.cpp
  479     RC = getMinimalPhysRegClass(Reg);
lib/Target/AArch64/AArch64InstrInfo.cpp
 3247                                               : TRI.getMinimalPhysRegClass(Reg);
lib/Target/AMDGPU/GCNRegBankReassign.cpp
  280   const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
  307   const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
  441   const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg);
lib/Target/AMDGPU/SIISelLowering.cpp
 2167     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  102       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
  135       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
  208         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
lib/Target/AVR/AVRAsmPrinter.cpp
  111       const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
lib/Target/AVR/AVRFrameLowering.cpp
  254     assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
  292     assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
lib/Target/Hexagon/BitTracker.cpp
  716   const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg);
lib/Target/Hexagon/HexagonBitTracker.cpp
  125   if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
lib/Target/Hexagon/HexagonExpandCondsets.cpp
  593     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
lib/Target/Hexagon/HexagonFrameLowering.cpp
 1270     const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
 1334     const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
 1516     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
 1528     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
lib/Target/Hexagon/HexagonInstrInfo.cpp
 1626       const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  707       predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
  719       predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
 1422       RC = HRI->getMinimalPhysRegClass(DepReg);
lib/Target/Hexagon/RDFCopy.cpp
   51       if (TRI.getMinimalPhysRegClass(DstR.Reg) !=
   52           TRI.getMinimalPhysRegClass(SrcR.Reg))
  123     const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg);
lib/Target/Mips/MipsFrameLowering.cpp
  127     unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
lib/Target/Mips/MipsSEFrameLowering.cpp
  262   const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst);
  834     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
lib/Target/PowerPC/PPCFrameLowering.cpp
 2260         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
 2418         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
   65           : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
   86     const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg);
lib/Target/X86/X86FrameLowering.cpp
 2041     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
 2124     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
 2203     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
lib/Target/XCore/XCoreFrameLowering.cpp
  440     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
  468     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);