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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/SelectionDAG.h 683 SDValue getRegister(unsigned Reg, EVT VT);
References
include/llvm/CodeGen/SelectionDAG.h 698 getRegister(Reg, N.getValueType()), N);
707 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
723 SDValue Ops[] = { Chain, getRegister(Reg, VT) };
733 SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 974 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
989 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
1909 DAG.getRegister(SwiftError.getOrCreateVRegUseAt(
7136 Entry.Node = DAG.getRegister(
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 3215 CurDAG->getRegister(RegNo, VT), nullptr));
3227 CurDAG->getRegister(RegNo, VT), nullptr));
lib/Target/AArch64/AArch64ISelLowering.cpp 4074 Ops.push_back(DAG.getRegister(RegToPass.first,
4232 DAG.getRegister(RetVal.first, RetVal.second.getValueType()));
4248 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
4257 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
4259 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
4463 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
4610 SDValue TEB = DAG.getRegister(AArch64::X18, MVT::i64);
6085 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
6087 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
8300 Chain, Callee, DAG.getRegister(AArch64::X15, MVT::i64),
10924 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
11099 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
lib/Target/AArch64/AArch64SelectionDAGInfo.cpp 75 TagSrc = DAG.getRegister(AArch64::SP, MVT::i64);
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 952 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
956 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
1470 TFI, CurDAG->getRegister(Info->getStackPtrOffsetReg(), MVT::i32));
1475 return std::make_pair(N, CurDAG->getRegister(Info->getScratchWaveOffsetReg(),
1488 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1504 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
1559 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1567 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
2071 CurDAG->getRegister(ST->isWave32() ? AMDGPU::EXEC_LO
2810 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
2814 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 4103 return DAG.getRegister(VReg, VT);
lib/Target/AMDGPU/R600ISelLowering.cpp 2153 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32);
2161 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32);
2204 Src = DAG.getRegister(ImmReg, MVT::i32);
lib/Target/AMDGPU/SIISelLowering.cpp 2298 SDValue ReturnAddrVirtualReg = DAG.getRegister(
2337 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2348 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2350 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2901 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
2940 Ops.push_back(DAG.getRegister(RegToPass.first,
4616 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
10259 SDValue VReg = DAG.getRegister(
10329 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT);
lib/Target/ARC/ARCISelDAGToDAG.cpp 54 Reg = CurDAG->getRegister(ARC::STATUS32, MVT::i32);
lib/Target/ARC/ARCISelLowering.cpp 340 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
400 SDValue StackPtr = DAG.getRegister(ARC::SP, MVT::i32);
669 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
lib/Target/ARM/ARMISelDAGToDAG.cpp 107 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
808 Offset = CurDAG->getRegister(0, MVT::i32);
827 Offset = CurDAG->getRegister(0, MVT::i32);
861 Offset = CurDAG->getRegister(0, MVT::i32);
877 Offset = CurDAG->getRegister(0, MVT::i32);
906 Offset = CurDAG->getRegister(0, MVT::i32);
1025 Offset = CurDAG->getRegister(0, MVT::i32);
1526 CurDAG->getRegister(0, MVT::i32), Chain };
1536 CurDAG->getRegister(0, MVT::i32), Chain };
1567 CurDAG->getRegister(0, MVT::i32), Chain };
1615 CurDAG->getRegister(0, MVT::i32), Chain };
1677 CurDAG->getRegister(0, MVT::i32), Chain};
1976 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2108 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2278 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2357 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2364 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2421 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2563 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2665 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2713 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2735 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2756 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2880 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2881 CurDAG->getRegister(0, MVT::i32) };
2884 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
2886 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};
2950 CurDAG->getRegister(ARM::SP, MVT::i32),
2953 CurDAG->getRegister(0, MVT::i32),
2997 CurDAG->getRegister(0, MVT::i32),
3007 CurDAG->getRegister(0, MVT::i32),
3048 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
3049 CurDAG->getRegister(0, MVT::i32) };
3076 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3095 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3140 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
3142 CurDAG->getRegister(0, MVT::i32)};
3147 CurDAG->getRegister(0, MVT::i32),
3148 CurDAG->getRegister(0, MVT::i32)};
3186 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
3199 CurDAG->getRegister(0, MVT::i32) };
3207 CurDAG->getRegister(0, MVT::i32)};
3214 CurDAG->getRegister(0, MVT::i32),
3215 CurDAG->getRegister(0, MVT::i32) };
3226 CurDAG->getRegister(0, MVT::i32)};
3233 CurDAG->getRegister(0, MVT::i32),
3234 CurDAG->getRegister(0, MVT::i32) };
3268 CurDAG->getRegister(0, MVT::i32) };
3416 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
3417 CurDAG->getRegister(0, MVT::i32) };
3421 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
3423 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};
3486 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3509 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3531 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3824 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3857 CurDAG->getRegister(0, MVT::i32), Chain};
3918 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4441 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4452 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4481 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4497 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4507 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4515 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4556 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4567 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4590 CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
4609 CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
4620 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4720 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
4756 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
lib/Target/ARM/ARMISelLowering.cpp 2398 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2798 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2804 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2819 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2830 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2839 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2841 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3115 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3614 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
4437 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4557 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4962 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
5009 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5044 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5151 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5200 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5254 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5263 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5280 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5799 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5843 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
6359 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
lib/Target/AVR/AVRISelDAGToDAG.cpp 381 SDValue RegZ = CurDAG->getRegister(AVR::R31R30, MVT::i16);
436 Ops.push_back(CurDAG->getRegister(AVR::R31R30, MVT::i16));
lib/Target/AVR/AVRISelLowering.cpp 1249 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1277 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1408 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
lib/Target/BPF/BPFISelDAGToDAG.cpp 216 SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64);
lib/Target/BPF/BPFISelLowering.cpp 386 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
442 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
lib/Target/Hexagon/HexagonISelLowering.cpp 221 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
506 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1096 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
2811 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
lib/Target/Lanai/LanaiISelDAGToDAG.cpp 132 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
145 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
lib/Target/Lanai/LanaiISelLowering.cpp 561 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
580 DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
748 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1141 DAG.getRegister(Lanai::R0, MVT::i32),
1175 DAG.getRegister(Lanai::R0, MVT::i32),
1218 DAG.getRegister(Lanai::R0, MVT::i32),
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 256 AM.Base.Reg = CurDAG->getRegister(MSP430::SR, MVT::i16);
lib/Target/MSP430/MSP430ISelLowering.cpp 755 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
771 RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
897 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
lib/Target/Mips/MipsISelDAGToDAG.cpp 69 return CurDAG->getRegister(GlobalBaseReg, getTargetLowering()->getPointerTy(
lib/Target/Mips/MipsISelLowering.cpp 148 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
670 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1920 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
2323 DAG.getRegister(Mips::ZERO, MVT::i32),
2356 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2437 DAG.getRegister(OffsetReg, Ty),
2438 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2942 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
3715 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3734 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
4219 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
lib/Target/Mips/MipsISelLowering.h 492 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 253 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
818 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
956 CurDAG->getRegister(Mips::HWR29, MVT::i32),
1040 SDValue ZeroVal = CurDAG->getRegister(
1064 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1086 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1142 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1199 SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 478 return CurDAG->getRegister(GlobalBaseReg,
2582 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
4141 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
4798 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
lib/Target/PowerPC/PPCISelLowering.cpp 2434 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2491 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2694 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
2696 ? DAG.getRegister(PPC::R2, VT)
2863 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2864 : DAG.getRegister(PPC::R2, MVT::i32);
2877 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2898 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2916 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
4895 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4897 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5115 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
5118 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
5133 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5146 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::X2
5232 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5294 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
5517 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5862 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
6424 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
6426 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
6930 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
6939 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
6949 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
6951 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
6953 RetOps.push_back(DAG.getRegister(*I, MVT::i1));
6955 RetOps.push_back(DAG.getRegister(*I, MVT::Other));
6998 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
9452 return DAG.getRegister(PPC::X13, MVT::i64);
9453 return DAG.getRegister(PPC::R2, MVT::i32);
9483 DAG.getRegister(PPC::CR6, MVT::i32),
14077 DAG.getRegister(PPC::CR6, MVT::i32),
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 72 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
lib/Target/RISCV/RISCVISelLowering.cpp 521 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
537 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
2297 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2424 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
2427 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
2440 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
lib/Target/Sparc/SparcISelDAGToDAG.cpp 70 return CurDAG->getRegister(GlobalBaseReg,
140 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));
235 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
282 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
357 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
lib/Target/Sparc/SparcISelLowering.cpp 253 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
276 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
357 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
822 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
843 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
877 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
886 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
915 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
958 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
1171 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1216 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1258 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2063 DAG.getRegister(SP::O0, PtrVT),
2104 DAG.getRegister(SP::G7, PtrVT), Offset,
2117 DAG.getRegister(SP::G7, PtrVT), Offset);
2513 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2997 return DAG.getRegister(SP::G7, PtrVT);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 629 Base = CurDAG->getRegister(0, VT);
657 Index = CurDAG->getRegister(0, VT);
lib/Target/SystemZ/SystemZISelLowering.cpp 1569 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1587 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1696 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
2884 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2885 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
lib/Target/X86/X86ISelDAGToDAG.cpp 278 Base = CurDAG->getRegister(0, VT);
293 Index = CurDAG->getRegister(0, VT);
323 Segment = CurDAG->getRegister(0, MVT::i16);
1388 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1391 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1467 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
1502 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
2229 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
2231 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
2233 AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
2272 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
2274 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
2276 AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
2405 Base = CurDAG->getRegister(0, MVT::i64);
2416 Index = CurDAG->getRegister(0, MVT::i64);
2444 SDValue T = CurDAG->getRegister(0, MVT::i32);
2535 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
2619 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy(DL)).getNode();
4933 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
lib/Target/X86/X86ISelLowering.cpp 2591 RetOps.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2638 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2651 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
4032 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
22248 DAG.getRegister(Vreg, SPTy));
23779 SDValue Segment = DAG.getRegister(0, MVT::i32);
24331 DAG.getRegister(StoreAddrReg, PtrVT));
26639 DAG.getRegister(X86::RSP, MVT::i64), // Base
26641 DAG.getRegister(0, MVT::i64), // Index
26643 DAG.getRegister(0, MVT::i16), // Segment.
26653 DAG.getRegister(X86::ESP, MVT::i32), // Base
26655 DAG.getRegister(0, MVT::i32), // Index
26657 DAG.getRegister(0, MVT::i16), // Segment.
lib/Target/XCore/XCoreISelDAGToDAG.cpp 119 Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
122 Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
lib/Target/XCore/XCoreISelLowering.cpp 849 DAG.getRegister(StackReg, MVT::i32),
850 DAG.getRegister(HandlerReg, MVT::i32));
1212 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1506 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
unittests/CodeGen/AArch64SelectionDAGTest.cpp 166 auto UnknownOp = DAG->getRegister(0, IntVT);
188 auto UnknownOp = DAG->getRegister(0, IntVT);