reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/SelectionDAG.h
  921   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,

References

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 3773     SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
 3857   return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
lib/Target/AArch64/AArch64ISelLowering.cpp
 2255     return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,
 2305     return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
 2367   Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
 4325   return DAG.getNode(
 4722     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
 4744           return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
 4760           return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
 4771         return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
 4781       return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
 4787     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
 4801       DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
 4804     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
 4979     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
 4999     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
 5009         DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
 5012     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
 5156     return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
 5191   SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
 5197     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
 5234     return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
 5618       DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
 5632   SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
 5643   SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
 5673       DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
 5687   SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
 5694   SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
 6901       Shuffle = DAG.getNode(
 7411       DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
 9313         return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
 9356   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
10282   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
11556   return DAG.getNode(NewOpc, DL, MVT::Other, N->getOperand(0), NewTestSrc,
lib/Target/AMDGPU/SIISelLowering.cpp
 5962     return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
 6006     return DAG.getNode(AMDGPUISD::FDOT2, DL, VT,
 7762       DisableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, MVT::Other,
 7773   SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32,
 7840   SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
 9762       return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc,
lib/Target/ARC/ARCISelLowering.cpp
  173   return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal,
lib/Target/ARM/ARMISelLowering.cpp
 3813   return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
 4970       return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
 5309     return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
lib/Target/AVR/AVRISelLowering.cpp
  630   return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
lib/Target/Lanai/LanaiISelLowering.cpp
  879   return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
lib/Target/MSP430/MSP430ISelLowering.cpp
 1124   return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
lib/Target/Mips/MipsISelLowering.cpp
  672   return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
  778   return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
  912     return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
  946       return DAG.getNode(
 2227     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
 2273     SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
 2322     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
 2355     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
 2436   return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
lib/Target/Mips/MipsSEISelLowering.cpp
 1980     return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
lib/Target/PowerPC/PPCISelLowering.cpp
 8155   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
lib/Target/Sparc/SparcISelLowering.cpp
 2460   return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
 2496   return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
   44   return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
lib/Target/X86/X86ISelDAGToDAG.cpp
 4343   SDValue Ternlog = CurDAG->getNode(X86ISD::VPTERNLOG, dl, NVT, A, B, C, Imm);
lib/Target/X86/X86ISelLowering.cpp
 9441             VT, DAG.getNode(X86ISD::VPERMIL2, DL, MVT::v8f32, LoLo, HiHi,
 9477             VT, DAG.getNode(X86ISD::VPERMIL2, DL, MVT::v4f64, LoLo, HiHi,
11927     return DAG.getNode(X86ISD::INSERTQI, DL, VT, V1 ? V1 : DAG.getUNDEF(VT),
21490       SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, T1.getValueType(), T2, T1,
22057           Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
22088             Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), Chain,
22133           Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
22149       Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
22181   return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
22861           return DAG.getNode(IntrWithRoundingModeOpcode, dl, Op.getValueType(),
22872       return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
23111           return DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
23130           Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::v1i1, Src1, Src2, CC, Sae);
23196         FCmp = DAG.getNode(X86ISD::FSETCCM_SAE, dl, MVT::v1i1, LHS, RHS,
23246       SDValue FixupImm = DAG.getNode(Opc, dl, VT, Src1, Src2, Src3, Imm);
23333       return DAG.getNode(IntrData->Opc1, dl, Op.getValueType(), Src, Rnd,
23965       return DAG.getNode(X86ISD::WRPKRU, dl, MVT::Other,
32537       Res = DAG.getNode(X86ISD::INSERTQI, DL, IntMaskVT, V1, V2,
32702     Res = DAG.getNode(X86ISD::VPERMIL2, DL, MaskVT, V1, V2, VPerm2MaskOp,
37788           DAG.getNode(X86ISD::CMOV, DL, VT, Diff, Add.getOperand(0),
42150   SDValue CMov = DAG.getNode(X86ISD::CMOV, DL, CMovVT, CMovOp0, CMovOp1,
42308   SDValue Res = DAG.getNode(X86ISD::CMOV, DL, ExtendVT, CMovOp0, CMovOp1,
42546     return DAG.getNode(NewOpcode, dl, VT, A, B, C, N->getOperand(3));
42568     return DAG.getNode(NewOpcode, dl, VT, N->getOperand(0), N->getOperand(1),