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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/SelectionDAG.h 932 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
References
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 2484 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2490 return DAG.getNode(ISD::ADDCARRY, DL,
2645 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2652 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2667 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2687 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2767 SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
2769 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
2809 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
2823 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
3153 return DAG.getNode(ISD::ADDCARRY, DL,
8875 return DAG.getNode(ISD::SETCC, SDLoc(N), N->getVTList(), LHS, RHS, Cond);
10799 return DAG.getNode(N0.getOpcode(), SL, VTs, X, Y, N0.getOperand(2));
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1017 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
3856 SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
lib/CodeGen/SelectionDAG/TargetLowering.cpp 5734 Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next,
5745 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
5748 Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
lib/Target/AArch64/AArch64ISelLowering.cpp 2344 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1706 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1708 SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1721 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1723 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1725 SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1735 SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1737 SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1755 SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1757 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1759 SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1775 SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1777 SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1779 SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
lib/Target/AMDGPU/SIISelLowering.cpp 5988 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
7688 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
7690 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
7717 EnableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, BindParamVTs,
7791 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
7803 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
9476 SDValue Mad = DAG.getNode(MadOpc, SL, VTs, N0, N1, N2);
lib/Target/ARM/ARMISelLowering.cpp 3563 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
4470 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
6123 Lo = DAG.getNode(ShPartsOpc, dl, DAG.getVTList(MVT::i32, MVT::i32), Lo, Hi,
6353 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
8696 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0),
8710 Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0),
11515 return DAG.getNode(Opcode, DL, N->getVTList(),
14337 Res = DAG.getNode(ISD::ADDCARRY, dl, VTs, Sub, Neg, Carry);
14392 Res = DAG.getNode(ISD::SUBCARRY, dl, VTs, FalseVal, Subc, Subc.getValue(1));
16197 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi,
lib/Target/Hexagon/HexagonISelLowering.cpp 685 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
lib/Target/PowerPC/PPCISelLowering.cpp15240 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
15255 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
lib/Target/Sparc/SparcISelLowering.cpp 2912 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2917 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
lib/Target/SystemZ/SystemZISelLowering.cpp 3537 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry);
lib/Target/X86/X86ISelLowering.cpp21107 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry.getValue(1));
21345 return DAG.getNode(X86ISD::SBB, DL, VTs, Zero, Zero, CmpZero);
21355 DAG.getNode(X86ISD::SBB, DL, VTs, Zero, Zero, Cmp);
23297 Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(2),
24027 SDValue Operation = DAG.getNode(Opcode, dl, VTs, Chain, Op.getOperand(2),
24055 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
26723 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(),
27269 SDValue Sum = DAG.getNode(Opc, DL, VTs, Op.getOperand(0),
27914 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi,
43481 return DAG.getNode(X86ISD::SBB, SDLoc(N), VTs,
43492 return DAG.getNode(X86ISD::SBB, SDLoc(N), N->getVTList(), Op0.getOperand(0),
43524 return DAG.getNode(X86ISD::ADC, SDLoc(N), VTs,
43604 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
43624 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
43682 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VTs, X,
43687 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VTs, X,
lib/Target/XCore/XCoreISelLowering.cpp 722 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
726 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
921 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
1643 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1731 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);