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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/SelectionDAG.h 930 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
References
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 2512 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2604 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2618 SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
2672 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2693 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
3250 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
3273 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
3287 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
3560 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
4188 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
4198 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
8487 SDValue UAO = DAG.getNode(ISD::UADDO, DL, VTs, Cond0, N2.getOperand(1));
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3206 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3224 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3237 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3298 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1052 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
2891 Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
3388 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow);
3393 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow);
3408 SDValue Five = DAG.getNode(ISD::UADDO, dl, VTFullAddO, Three, Four);
3772 SDValue LowCmp = DAG.getNode(ISD::USUBO, dl, VTList, LHSLo, RHSLo);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 272 SDNode *ScalarNode = DAG.getNode(
1427 SDNode *LoNode = DAG.getNode(Opcode, dl, LoVTs, LoLHS, LoRHS).getNode();
1428 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode();
3238 SDNode *WideNode = DAG.getNode(
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 9210 SDValue Res = getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 5678 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
6540 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
lib/CodeGen/SelectionDAG/TargetLowering.cpp 4715 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor);
4835 DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y);
5620 Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
5731 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
6925 SDValue Result = DAG.getNode(OverflowOp, dl, DAG.getVTList(VT, BoolVT),
6989 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
7003 DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
7024 SDValue Result = DAG.getNode(LoHiOp, dl, DAG.getVTList(VT, VT), LHS, RHS);
7212 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
lib/Target/AArch64/AArch64ISelLowering.cpp 1643 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
2164 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
2176 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
2192 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
2198 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
2210 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
2343 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
2371 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
6829 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
6832 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
6835 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
6838 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
6841 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
6844 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
7681 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), LHS,
7684 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), LHS,
9311 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1657 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1981 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
2001 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
2785 return DAG.getNode(NewOpcode, SDLoc(Node24), Node24->getVTList(),
3267 SDValue Mul = DAG.getNode(MulOpc, SL,
lib/Target/AMDGPU/R600ISelLowering.cpp 822 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
860 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
878 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
lib/Target/AMDGPU/SIISelLowering.cpp 7712 EnableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, BindParamVTs,
lib/Target/ARM/ARMISelLowering.cpp 4279 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4385 Value = DAG.getNode(ARMISD::ADDC, dl,
4403 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4414 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4448 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4458 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4493 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4498 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4509 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
5591 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
7659 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
7663 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
7667 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
7879 return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2)
7923 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
8722 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry);
8796 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
11489 return DAG.getNode(Opcode, DL, N->getVTList(), N->getOperand(0), RHS);
14331 SDValue Neg = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, Sub);
14344 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
14358 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
14391 SDValue Subc = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, TrueVal);
16091 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
16196 Lo = DAG.getNode(ISD::UADDO, dl, VTList, Tmp, Lo);
lib/Target/PowerPC/PPCISelLowering.cpp 7094 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
10212 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
13169 SDValue Swap = DAG.getNode(
13178 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other),
13239 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
15238 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
15253 SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
lib/Target/Sparc/SparcISelLowering.cpp 2915 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
lib/Target/SystemZ/SystemZISelLowering.cpp 3471 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
3477 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3543 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3942 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
lib/Target/X86/X86ISelLowering.cpp20111 return DAG.getNode(X86ISD::SUB, dl, VTs, Op->getOperand(0),
20183 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, Op0, Op1);
21103 Carry = DAG.getNode(X86ISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32),
21154 Value = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
21173 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC);
22251 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Size);
23292 Res = DAG.getNode(IntrData->Opc1, dl, VTs, Op.getOperand(2),
23295 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(1),
23604 DAG.getNode(X86ISD::VP2INTERSECT, DL, VTs,
23958 return DAG.getNode(X86ISD::RDPKRU, dl, VTs, Op.getOperand(0),
24009 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
24030 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
24130 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
24347 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
24953 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
27180 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
27187 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
27195 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
27265 Carry = DAG.getNode(X86ISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32),
27276 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
27330 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
27913 Lo = DAG.getNode(ISD::UADDO, dl, VTList, Tmp, Lo);
37543 DAG.getNode(X86ISD::SUB, SDLoc(CarryOp1), CarryOp1->getVTList(),
39096 SDValue Flags = DAG.getNode(X86ISD::XOR, DL, VTs, Lo, Hi).getValue(1);
43432 Op = DAG.getNode(NewOpc, dl, VTs, Op0, Op1);
43590 SDValue NewSub = DAG.getNode(
43620 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
43653 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, X86SubVTs, Zero, Z);