reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/SelectionDAG.h

  929   SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N);

References

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1101       NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
 3122       Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 2853   SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 6186     Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
 6340     Res = DAG.getNode(
 6360     Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),

lib/Target/AMDGPU/R600ISelLowering.cpp

 1964         return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),

lib/Target/ARM/ARMISelLowering.cpp

 2027   SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
 2791         SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
 2813       SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
 4664     FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
 4666     TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
 5502     Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
 5518   Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
 5759       Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
 5763       Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
 6147   Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);

lib/Target/Hexagon/HexagonISelLowering.cpp

  643   return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);

lib/Target/Mips/MipsISelLowering.h

  493           DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));

lib/Target/PowerPC/PPCISelLowering.cpp

10195     SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));

lib/Target/RISCV/RISCVISelLowering.cpp

  873         DAG.getNode(RISCVISD::READ_CYCLE_WIDE, DL, VTs, N->getOperand(0));
  957         DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32),
 2165       SDValue SplitF64 = DAG.getNode(
 2408       SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL,

lib/Target/X86/X86ISelLowering.cpp

24044     SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
24126     SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
24783   Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
24814   Op = DAG.getNode(X86ISD::BSF, dl, VTs, N0);