reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1013 const MCInstrDesc &MCID = MI.getDesc(); 1020 if (MI.isCopy()) { 1021 CopyDstReg = MI.getOperand(0).getReg(); 1022 CopySrcReg = MI.getOperand(1).getReg(); 1023 CopyDstSub = MI.getOperand(0).getSubReg(); 1024 CopySrcSub = MI.getOperand(1).getSubReg(); 1038 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1039 MachineOperand &MO = MI.getOperand(i); 1056 if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) 1065 definePhysReg(MI, Reg, 1081 if (MI.isInlineAsm() || hasEarlyClobbers || hasPartialRedefs || 1083 handleThroughOperands(MI, VirtDead); 1095 MachineOperand &MO = MI.getOperand(I); 1111 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg); 1114 if (setPhysReg(MI, MO, PhysReg)) 1123 for (MachineOperand &MO : MI.uses()) { 1139 for (const MachineOperand &MO : MI.operands()) { 1150 unsigned DefOpEnd = MI.getNumOperands(); 1151 if (MI.isCall()) { 1160 spillAll(MI, /*OnlyLiveOut*/ false); 1166 const MachineOperand &MO = MI.getOperand(I); 1173 definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved); 1179 const MachineOperand &MO = MI.getOperand(I); 1187 MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg); 1188 if (setPhysReg(MI, MI.getOperand(I), PhysReg)) { 1188 if (setPhysReg(MI, MI.getOperand(I), PhysReg)) { 1203 LLVM_DEBUG(dbgs() << "<< " << MI); 1206 Coalesced.push_back(&MI);