reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/MachineInstr.h

 1548   void addOperand(MachineFunction &MF, const MachineOperand &Op);

References

include/llvm/CodeGen/MachineInstrBuilder.h

   92     MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
  123     MI->addOperand(*MF, MachineOperand::CreateImm(Val));
  128     MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
  133     MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
  139     MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
  144     MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
  151     MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
  157     MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
  164     MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
  171     MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
  177     MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
  184     MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
  189     MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
  216     MI->addOperand(*MF, MO);
  222       MI->addOperand(*MF, MO);
  228     MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
  239     MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
  244     MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
  249     MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
  254     MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val));
  260     MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));

lib/CodeGen/MIRParser/MIParser.cpp

  981     MI->addOperand(MF, Operand.Operand);

lib/CodeGen/MachineInstr.cpp

  106       addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
  110       addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
  143     addOperand(MF, MO);
  181   addOperand(*MF, Op);
  208     return addOperand(MF, CopyOp);
 1404       addOperand(MF, MO);

lib/CodeGen/StackMapLivenessAnalysis.cpp

  155   MI.addOperand(MF, MO);

lib/Target/AArch64/AArch64InstructionSelector.cpp

 1123   MovZ->addOperand(MF, I.getOperand(1));
 1126   MovZ->addOperand(MF, MachineOperand::CreateImm(0));
 1136       MovI->addOperand(MF, MachineOperand::CreateGA(
 1139       MovI->addOperand(
 1143     MovI->addOperand(MF, MachineOperand::CreateImm(Offset));

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  323       I.addOperand(*MF, MachineOperand::CreateImm(0));
  324       I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
  411     I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
  412     I.addOperand(*MF, MachineOperand::CreateImm(0));
 1606     I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));

lib/Target/AMDGPU/SIFixVGPRCopies.cpp

   59           MI.addOperand(MF,

lib/Target/AMDGPU/SIFixupVectorISel.cpp

  188       NewGlob->addOperand(MF, MI.getOperand(0));
  189     NewGlob->addOperand(MF, MachineOperand::CreateReg(IndexReg, false));
  191       NewGlob->addOperand(MF, *VData);
  192     NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false));
  198       NewGlob->addOperand(MF, *Glc);
  202       NewGlob->addOperand(MF, *DLC);
  209       NewGlob->addOperand(MF, *VDstInOp);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  178       NewMI.addOperand(MF, MO);

lib/Target/PowerPC/PPCInstrInfo.cpp

 1983           MI->addOperand(*MI->getParent()->getParent(),
 1989           MI->addOperand(*MI->getParent()->getParent(),

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

 1335             MI.addOperand(MF, MO);

lib/Target/X86/X86FlagsCopyLowering.cpp

  327         MI.addOperand(MF, OpV);
  328         MI.addOperand(MF, MachineOperand::CreateMBB(&NewMBB));

lib/Target/X86/X86SpeculativeLoadHardening.cpp

  304       MI.addOperand(MF, OpV);
  305       MI.addOperand(MF, MachineOperand::CreateMBB(&NewMBB));

unittests/CodeGen/MachineInstrTest.cpp

  187   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
  188   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
  191   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
  192   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
  207   MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
  208   MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
  211   MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
  212   MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
  260   VD1VU->addOperand(*MF,
  262   VD1VU->addOperand(*MF,
  266   VD2VU->addOperand(*MF,
  268   VD2VU->addOperand(*MF,
  272   VD1SU->addOperand(*MF,
  274   VD1SU->addOperand(*MF,
  278   VD1SD->addOperand(*MF,
  280   VD1SD->addOperand(*MF,
  284   VD2PU->addOperand(*MF,
  286   VD2PU->addOperand(*MF,
  290   VD2PD->addOperand(*MF,
  292   VD2PD->addOperand(*MF,
  331   MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));