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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/GlobalISel/Utils.h 92 bool constrainSelectedInstRegOperands(MachineInstr &I,
References
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 969 constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
include/llvm/CodeGen/MachineInstrBuilder.h 311 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
lib/Target/AArch64/AArch64InstructionSelector.cpp 1034 constrainSelectedInstRegOperands(*UShl, TII, TRI, RBI);
1076 constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI);
1078 constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI);
1102 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1110 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1127 constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);
1144 constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
1230 return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
1330 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1422 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
1428 constrainSelectedInstRegOperands(*CMP.getInstr(), TII, TRI, RBI);
1435 return constrainSelectedInstRegOperands(*Bcc.getInstr(), TII, TRI, RBI);
1441 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1481 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1576 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1625 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1636 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1657 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1671 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1686 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1713 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1737 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1814 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1818 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1847 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1883 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1915 constrainSelectedInstRegOperands(*AddsMI, TII, TRI, RBI);
1925 constrainSelectedInstRegOperands(*CsetMI, TII, TRI, RBI);
1939 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1995 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2122 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
2138 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2184 constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI);
2185 constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI);
2263 constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
2264 constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
2266 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
2267 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
2304 return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
2366 return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
2452 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2507 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
2668 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
2673 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
2692 constrainSelectedInstRegOperands(*Undef, TII, TRI, RBI);
2693 constrainSelectedInstRegOperands(*Ins, TII, TRI, RBI);
2737 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
2738 constrainSelectedInstRegOperands(*Ins2MI, TII, TRI, RBI);
2772 constrainSelectedInstRegOperands(SubRegMI, TII, TRI, RBI);
2773 constrainSelectedInstRegOperands(SubRegMI2, TII, TRI, RBI);
2774 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI);
2857 constrainSelectedInstRegOperands(*LaneCopyMI, TII, TRI, RBI);
3005 constrainSelectedInstRegOperands(ImpDefMI, TII, TRI, RBI);
3006 constrainSelectedInstRegOperands(InsMI, TII, TRI, RBI);
3020 constrainSelectedInstRegOperands(*FirstCopy, TII, TRI, RBI);
3030 constrainSelectedInstRegOperands(CopyInst, TII, TRI, RBI);
3104 constrainSelectedInstRegOperands(*Adrp, TII, TRI, RBI);
3105 constrainSelectedInstRegOperands(*LoadMI, TII, TRI, RBI);
3165 constrainSelectedInstRegOperands(*AddMI, TII, TRI, RBI);
3191 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
3219 constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
3267 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
3327 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
3360 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
3374 constrainSelectedInstRegOperands(*I, TII, TRI, RBI);
3461 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
3470 constrainSelectedInstRegOperands(*CSel, TII, TRI, RBI);
3634 constrainSelectedInstRegOperands(*Dup, TII, TRI, RBI);
3713 constrainSelectedInstRegOperands(*TBL1, TII, TRI, RBI);
3736 constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
3737 constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);
3769 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
3842 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
3918 constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI);
3997 constrainSelectedInstRegOperands(*SHA1Inst, TII, TRI, RBI);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 293 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
317 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
325 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
338 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
378 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI))
413 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
736 constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) &&
752 bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
1029 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1050 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
1067 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
1116 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) |
1117 constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI);
1134 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
1271 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
1288 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
1298 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
1391 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
1430 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 1320 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
lib/Target/ARM/ARMInstructionSelector.cpp 583 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
591 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
602 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
701 if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI))
708 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
715 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
730 if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI))
741 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
763 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
780 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
796 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
809 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
890 if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
938 if (!constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI))
1111 if (!constrainSelectedInstRegOperands(*AndI, TII, TRI, RBI))
1145 if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI))
1153 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
1173 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
lib/Target/Mips/MipsInstructionSelector.cpp 136 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
142 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
148 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
156 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
158 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
249 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
273 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
279 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
322 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI))
330 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
341 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI))
352 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
359 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
434 if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
441 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
539 if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
545 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
570 if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI))
583 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
593 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
602 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
770 if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI))
778 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
798 if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI))
805 if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI))
816 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
lib/Target/Mips/MipsLegalizerInfo.cpp 359 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
lib/Target/X86/X86InstructionSelector.cpp 546 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
583 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
629 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
676 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
875 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI);
980 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
981 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
1047 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1048 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
1049 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI);
1050 constrainSelectedInstRegOperands(Set3, TII, TRI, RBI);
1072 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1073 constrainSelectedInstRegOperands(Set, TII, TRI, RBI);
1129 if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) ||
1191 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1325 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1417 constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
1484 constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI);