reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/ADT/APInt.h

  956       int64_t SExtVAL = SignExtend64(U.VAL, BitWidth);
 1589       return SignExtend64(U.VAL, BitWidth);

include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

  621         Value = SignExtend64(Value, Ty.getSizeInBits());

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 1365     Offset = SignExtend64(Offset, BitWidth);

lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h

   98       Addend = SignExtend64(Addend, 28);
  111       Addend = SignExtend64(Addend, 33);
  297       ExplicitAddend = SignExtend64(RawAddend, 24);
  500       SignExtend64(readBytesUnaligned(LocalAddress, NumBytes), NumBytes * 8);

lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h

  171       SignExtend64(readBytesUnaligned(LocalAddress, NumBytes), NumBytes * 8);

lib/Support/APInt.cpp

  286     int64_t lhsSext = SignExtend64(U.VAL, BitWidth);
  287     int64_t rhsSext = SignExtend64(RHS.U.VAL, BitWidth);
  814       int64_t sext = SignExtend64(getWord(0), BitWidth);
  892     return APInt(Width, SignExtend64(U.VAL, BitWidth));
  901       SignExtend64(Result.U.pVal[getNumWords() - 1],
  981     U.pVal[getNumWords() - 1] = SignExtend64(
  997           SignExtend64(U.pVal[WordsToMove - 1], APINT_BITS_PER_WORD - BitShift);

lib/Target/AArch64/AArch64InstrInfo.cpp

 4178     uint64_t UImm = SignExtend64(Imm, BitSize);
 4269     uint64_t UImm = SignExtend64(-Imm, BitSize);

lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

  245         << formatImm(SignExtend64(Value, RegWidth));
  260         << formatImm(SignExtend64(Value, RegWidth));
  274         << formatImm(SignExtend64(Value, RegWidth));

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

 1660         ImmField = SignExtend64(COffsetVal, NumBits);

lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

  397     int64_t Extended = SignExtend64(Value, 32);

lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

  733   tmp = SignExtend64(tmp, Bits);
  746   uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

  676   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  713     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
  720     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  725     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
  749   int64_t  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  786     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
  793     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  798     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
  819   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  858   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  901   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  946   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
  988   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 1037   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 2559     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 2564     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 2570     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 2606     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 2610     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 2615     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

  924     uint64_t SextImm = SignExtend64(Lo, 16);
 1095     uint64_t SextImm = SignExtend64(Imm, MinSize);

lib/Target/PowerPC/PPCISelLowering.cpp

13477       uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1),

lib/Target/RISCV/Utils/RISCVMatInt.cpp

   69   Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);

lib/Target/SystemZ/SystemZISelLowering.cpp

  699     int64_t SignedValue = SignExtend64(Value, SplatBitSize);

lib/Transforms/InstCombine/InstCombineCompares.cpp

  497   Offset = SignExtend64(Offset, IntPtrWidth);
  498   VariableScale = SignExtend64(VariableScale, IntPtrWidth);

tools/lld/ELF/Arch/RISCV.cpp

  285     int64_t imm = SignExtend64(val + 0x800, bits) >> 12;
  330     int64_t hi = SignExtend64(val + 0x800, bits) >> 12;
  346     checkInt(loc, SignExtend64(hi, bits) >> 12, 20, type);

tools/lld/ELF/InputSection.cpp

  897     uint64_t targetVA = SignExtend64(rel.sym->getVA(rel.addend), bits);
  934     uint64_t targetVA = SignExtend64(

tools/lld/ELF/Target.h

  208   if (v != llvm::SignExtend64(v, n))
  222   if (v != (uint64_t)llvm::SignExtend64(v, n) && (v >> n) != 0)

tools/lldb/source/Symbol/ClangASTContext.cpp

 9406     val = llvm::SignExtend64(val, 8*byte_size);

tools/lldb/source/Utility/DataExtractor.cpp

  574   return llvm::SignExtend64(u64, 8 * byte_size);