|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Overridden By
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc17772 unsigned resolveVariantSchedClass(unsigned SchedClass,
22889 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc 631 unsigned resolveVariantSchedClass(unsigned SchedClass,
859 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/AMDGPU/R600GenSubtargetInfo.inc 244 unsigned resolveVariantSchedClass(unsigned SchedClass,
344 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/ARC/ARCGenSubtargetInfo.inc 92 unsigned resolveVariantSchedClass(unsigned SchedClass,
167 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc19351 unsigned resolveVariantSchedClass(unsigned SchedClass,
23256 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/AVR/AVRGenSubtargetInfo.inc 440 unsigned resolveVariantSchedClass(unsigned SchedClass,
568 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/BPF/BPFGenSubtargetInfo.inc 110 unsigned resolveVariantSchedClass(unsigned SchedClass,
190 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Hexagon/HexagonGenSubtargetInfo.inc 4607 unsigned resolveVariantSchedClass(unsigned SchedClass,
4718 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Lanai/LanaiGenSubtargetInfo.inc 173 unsigned resolveVariantSchedClass(unsigned SchedClass,
251 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/MSP430/MSP430GenSubtargetInfo.inc 110 unsigned resolveVariantSchedClass(unsigned SchedClass,
191 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Mips/MipsGenSubtargetInfo.inc 3767 unsigned resolveVariantSchedClass(unsigned SchedClass,
4056 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc 164 unsigned resolveVariantSchedClass(unsigned SchedClass,
266 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/PowerPC/PPCGenSubtargetInfo.inc 8089 unsigned resolveVariantSchedClass(unsigned SchedClass,
8246 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 181 unsigned resolveVariantSchedClass(unsigned SchedClass,
305 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Sparc/SparcGenSubtargetInfo.inc 464 unsigned resolveVariantSchedClass(unsigned SchedClass,
563 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/SystemZ/SystemZGenSubtargetInfo.inc 5093 unsigned resolveVariantSchedClass(unsigned SchedClass,
5205 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc 122 unsigned resolveVariantSchedClass(unsigned SchedClass,
209 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/X86/X86GenSubtargetInfo.inc21319 unsigned resolveVariantSchedClass(unsigned SchedClass,
22913 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/XCore/XCoreGenSubtargetInfo.inc 93 unsigned resolveVariantSchedClass(unsigned SchedClass,
168 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
References
lib/MC/MCSchedule.cpp 77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
lib/MCA/InstrBuilder.cpp 526 SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID);
tools/llvm-exegesis/lib/SchedClassResolution.cpp 225 STI.resolveVariantSchedClass(SchedClassId, &MCI, SM.getProcessorID());
tools/llvm-mca/Views/InstructionInfoView.cpp 49 SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, CPUID);