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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 4979 RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
4986 RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
20382 mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
20389 mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17252 RI->mapDwarfRegsToLLVMRegs(AMDGPUDwarfFlavour0Dwarf2L, AMDGPUDwarfFlavour0Dwarf2LSize, false);
17259 RI->mapDwarfRegsToLLVMRegs(AMDGPUEHFlavour0Dwarf2L, AMDGPUEHFlavour0Dwarf2LSize, true);
48743 mapDwarfRegsToLLVMRegs(AMDGPUDwarfFlavour0Dwarf2L, AMDGPUDwarfFlavour0Dwarf2LSize, false);
48750 mapDwarfRegsToLLVMRegs(AMDGPUEHFlavour0Dwarf2L, AMDGPUEHFlavour0Dwarf2LSize, true);
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 462 RI->mapDwarfRegsToLLVMRegs(ARCDwarfFlavour0Dwarf2L, ARCDwarfFlavour0Dwarf2LSize, false);
469 RI->mapDwarfRegsToLLVMRegs(ARCEHFlavour0Dwarf2L, ARCEHFlavour0Dwarf2LSize, true);
819 mapDwarfRegsToLLVMRegs(ARCDwarfFlavour0Dwarf2L, ARCDwarfFlavour0Dwarf2LSize, false);
826 mapDwarfRegsToLLVMRegs(ARCEHFlavour0Dwarf2L, ARCEHFlavour0Dwarf2LSize, true);
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3531 RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
3538 RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
15977 mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
15984 mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 806 RI->mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
813 RI->mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
1719 mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
1726 mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 336 RI->mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
343 RI->mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
705 mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
712 mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2221 RI->mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
2228 RI->mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
3682 mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
3689 mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 517 RI->mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
524 RI->mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
931 mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
938 mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3759 RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3766 RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
7374 mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
7381 mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3781 RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
3784 RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
3791 RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
3794 RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
5700 mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
5703 mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
5710 mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
5713 mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1064 RI->mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false);
1071 RI->mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true);
1834 mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false);
1841 mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true);
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 1837 RI->mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
1844 RI->mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
2799 mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
2806 mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 1731 RI->mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
1738 RI->mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
2965 mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
2972 mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
gen/lib/Target/X86/X86GenRegisterInfo.inc 4237 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
4240 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
4243 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
4250 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
4253 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
4256 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
9948 mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
9951 mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
9954 mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
9961 mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
9964 mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
9967 mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 283 RI->mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
290 RI->mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);
577 mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
584 mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);