reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/RegisterPressure.h

  324     I->LaneMask &= ~Pair.LaneMask;

include/llvm/MC/LaneBitmask.h

   83     static constexpr LaneBitmask getAll() { return ~LaneBitmask(0); }

lib/CodeGen/DetectDeadLanes.cpp

  210   if ((UsedLanes & ~PrevUsedLanes).none())
  257       MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
  303   if ((DefinedLanes & ~PrevDefinedLanes).none())
  329       DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);

lib/CodeGen/LiveInterval.cpp

  942       SR.LaneMask = SRMask & ~Matching;
  951     ToApply &= ~Matching;
  981     LaneBitmask UndefMask = VRegMask & ~DefMask;
 1089     assert((Mask & ~MaxMask).none());

lib/CodeGen/LiveIntervals.cpp

  784             if ((UseMask & ~DefinedLanesMask).any())

lib/CodeGen/LiveRangeCalc.cpp

  181         SLM = ~SLM;

lib/CodeGen/MachineBasicBlock.cpp

  454   I->LaneMask &= ~LaneMask;

lib/CodeGen/MachineVerifier.cpp

 2567           SLM = ~SLM;
 2692     if ((SR.LaneMask & ~MaxMask).any()) {

lib/CodeGen/RegisterCoalescer.cpp

 1392         MaxMask &= ~SR.LaneMask;
 1629     Mask = ~Mask;
 2617       OtherV.ValidLanes &= ~OtherV.WriteLanes;
 2641     V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
 2700   if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes).none())
 2750         (OtherV.WriteLanes & ~V.ValidLanes).any()) {
 2816     TaintedLanes &= ~OV.WriteLanes;
 3736             assert((S.LaneMask & ~MaxMask).none());

lib/CodeGen/RegisterPressure.cpp

   53   assert((PrevMask & ~NewMask).none() && "Must not remove bits");
  415     I->LaneMask &= ~Pair.LaneMask;
  610         AddFlagsMI != nullptr && (LiveAfter & ~I->LaneMask).none())
  776     LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
  778     LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
  916     LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
  927         decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
 1067     LaneBitmask LiveAfter = (LiveLanes & ~DefLanes) | UseLanes;
 1235       LastUseMask &= ~UseMask;
 1313       LaneBitmask NewMask = LiveMask & ~LastUseMask;

lib/CodeGen/ScheduleDAGInstrs.cpp

  410           KillLaneMask &= ~getLaneMaskForMO(OtherMO);
  446       LaneMask &= ~KillLaneMask;
  491     LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;

lib/CodeGen/SplitKit.cpp

  574     if ((SubRegMask & ~LaneMask).any())
  594   LaneBitmask LanesLeft = LaneMask & ~(TRI.getSubRegIndexLaneMask(BestIdx));
  609                 - (SubRegMask & ~LanesLeft).getNumLanes();
  621     LanesLeft &= ~TRI.getSubRegIndexLaneMask(BestIdx);

lib/Target/AMDGPU/GCNRegPressure.cpp

  127       Sign * (~PrevMask & NewMask).getNumLanes();
  340     LiveMask &= ~getDefRegMask(MO, *MRI);
  384           It.second &= ~S.LaneMask;

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  175     if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
  193     if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
  197     LaneMask &= ~SubRegMask;

lib/Target/Hexagon/RDFRegisters.cpp

  189     M &= ~SM;

utils/TableGen/CodeGenRegisters.cpp

 1530       CoveringLanes &= ~Mask;