reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/ExecutionDomainFix.cpp

  248       LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
  340     const int Def = RDA->getReachingDef(mi, RC->getRegister(rx));
  342       return RDA->getReachingDef(mi, RC->getRegister(I)) <= Def;
  446       for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid();

lib/Target/AArch64/AArch64AsmPrinter.cpp

  554   unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));

lib/Target/AArch64/AArch64ISelLowering.cpp

 6043           Res.first = AArch64::FPR64RegClass.getRegister(RegNo);
 6046           Res.first = AArch64::FPR128RegClass.getRegister(RegNo);

lib/Target/AArch64/AArch64RegisterInfo.cpp

   92       UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
  159       for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i),
  207       markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));

lib/Target/AMDGPU/R600EmitClauseMarkers.cpp

  179             R600::R600_KC0RegClass.getRegister(UsedKCache[j].second));
  183             R600::R600_KC1RegClass.getRegister(UsedKCache[j].second));

lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp

  144               R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
  244           DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);

lib/Target/AMDGPU/R600InstrInfo.cpp

 1043                       getIndirectAddrRegClass()->getRegister(Address));
 1056         buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
 1103       unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
 1128     case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
 1129     case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
 1130     case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
 1131     case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
 1160     case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
 1161     case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
 1162     case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
 1163     case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
 1202       if (IndirectRC->getRegister(RegIndex) == Reg)

lib/Target/AMDGPU/SIISelLowering.cpp

10651         return std::make_pair(RC->getRegister(Idx), RC);

lib/Target/AMDGPU/SIRegisterInfo.cpp

  112   unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
  136   return AMDGPU::SGPR_32RegClass.getRegister(Reg);
  195     unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
  202     unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
  204     Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
  211       unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  296   MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase));

lib/Target/ARM/ARMBaseInstrInfo.cpp

 2469     unsigned CurReg = RegClass->getRegister(CurRegEnc);

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

   79   return Mips::MSACtrlRegClass.getRegister(RegNum);