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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 679 return TLI.isOperationLegal(Opcode, VT);
1132 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1138 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
2139 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2140 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2308 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2848 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
2901 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
3983 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4039 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4115 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4158 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4229 if (!TLI.isOperationLegal(Opcode, VT) &&
4240 if (TLI.isOperationLegal(AltOpcode, VT))
4304 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4551 TLI.isOperationLegal(ISD::SETCC, OpVT))))
5837 if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) &&
6495 if (LegalOperations && !TLI.isOperationLegal(ISD::STORE, VT))
6588 if (NeedsBswap && LegalOperations && !TLI.isOperationLegal(ISD::BSWAP, VT))
6662 if (LegalOperations && !TLI.isOperationLegal(ISD::LOAD, VT))
6753 if (NeedsBswap && LegalOperations && !TLI.isOperationLegal(ISD::BSWAP, VT))
7571 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
8062 if (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ_ZERO_UNDEF, VT)) {
8089 if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_UNDEF, VT)) {
8492 if (TLI.isOperationLegal(ISD::SELECT_CC, VT) ||
9168 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT)))
9175 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT)))
9462 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
9500 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
9606 (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT))) {
9614 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
9749 if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
9750 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
9761 if (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) {
9813 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
10405 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
10415 TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT))
10425 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
10614 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
10626 (!LegalOperations || TLI.isOperationLegal(ISD::SHL, VT)) &&
10772 TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecSrcVT))) {
10794 TLI.isOperationLegal(N0.getOpcode(), VT))) {
10838 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) {
10883 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
10979 TLI.isOperationLegal(ISD::ConstantFP, VT)) ||
10981 TLI.isOperationLegal(ISD::Constant, VT))) {
11004 TLI.isOperationLegal(ISD::LOAD, VT))) {
11333 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
11544 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
11852 (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
12144 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
12257 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
12273 TLI.isOperationLegal(ISD::FABS, VT)) {
12304 TLI.isOperationLegal(ISD::FNEG, VT))
12401 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
12410 (TLI.isOperationLegal(ISD::ConstantFP, VT) ||
12552 TLI.isOperationLegal(ISD::ConstantFP, VT) ||
12680 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
12683 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
12805 if (!TLI.isOperationLegal(ISD::FTRUNC, VT) ||
13204 TLI.isOperationLegal(ISD::ConstantFP, VT)))
13890 TLI.isOperationLegal(ISD::FTRUNC, STMemType)) {
14328 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
14342 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
14348 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
14431 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
14451 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
14979 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
14980 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
16141 TLI.isOperationLegal(ISD::STORE, SVT)) &&
16642 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
16926 TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecVT) ||
17153 (!TLI.isOperationLegal(ISD::BUILD_VECTOR, VecVT) &&
17154 TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)))
17216 !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1))
17374 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
18304 TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) &&
20070 TLI.isOperationLegal(ISD::SHL, VT) &&
20071 TLI.isOperationLegal(ISD::SRA, VT)) {
20100 (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT))) {
20160 (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ, VT)))
20167 (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT)))
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 500 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
505 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) &&
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1639 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1672 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1696 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
3333 (isOperationLegal(ISD::SETCC, newVT) &&
4709 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT)
4712 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT)
4829 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT)
4832 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT)
5368 return isOperationLegal(ISD::ConstantFP, VT) ||
5380 if (isOperationLegal(ISD::ConstantFP, VT) &&
5381 isOperationLegal(ISD::BUILD_VECTOR, VT))
5848 if (isOperationLegal(RevRot, VT)) {
6316 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
6316 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
lib/CodeGen/SwitchLoweringUtils.cpp 281 if (!TLI->isOperationLegal(ISD::SHL, PTy))
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 3038 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) {
lib/Target/AMDGPU/R600ISelLowering.cpp 1910 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
lib/Target/AMDGPU/SIISelLowering.cpp 9416 isOperationLegal(ISD::FMAD, VT))
lib/Target/ARM/ARMISelLowering.cpp11532 if (TLI.isOperationLegal(N->getOpcode(), N->getValueType(0)))
lib/Target/PowerPC/PPCISelLowering.cpp15123 if (VT.isVector() && TLI.isOperationLegal(Opcode, VT) &&
15331 isOperationLegal(ISD::MUL, N->getValueType(0)))
lib/Target/SystemZ/SystemZISelLowering.cpp 4741 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
lib/Target/X86/X86ISelLowering.cpp 4944 if (isOperationLegal(ISD::MUL, VT))
7923 if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT))
20803 TLI.isOperationLegal(ISD::UMIN, VT)) {
24923 if (Opcode == ISD::UADDSAT && !TLI.isOperationLegal(ISD::UMIN, VT)) {
24929 if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) {
39049 if (TLI.isTypeLegal(VT) && TLI.isOperationLegal(ISD::CTPOP, VT))
39394 if (!DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT))
41000 TLI.isOperationLegal(SrcOpcode, VT) &&
41001 !TLI.isOperationLegal(SrcOpcode, SrcVT))
41007 if (TLI.isOperationLegal(SrcOpcode, VT) &&
41017 if (TLI.isOperationLegal(SrcOpcode, VT) &&
lib/Target/X86/X86TargetTransformInfo.cpp 3399 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);