reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Overridden By

lib/Target/AMDGPU/SIISelLowering.cpp

10937 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {

lib/Target/ARM/ARMISelLowering.cpp

 1692 ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {

References

lib/CodeGen/CallingConvLower.cpp

  251     const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);

lib/CodeGen/MachineScheduler.cpp

 2759         TLI->getRegClassFor(LegalIntVT));

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14427         TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent());
14429         TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT(),

lib/CodeGen/SelectionDAG/FastISel.cpp

  445     Reg = createResultReg(TLI.getRegClassFor(VT));
  942     CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
 1550     const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
 1551     const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
 2229   unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));

lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

  352       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  108     UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
  167     DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
  210       const TargetRegisterClass *VTRC = TLI->getRegClassFor(
  273     const TargetRegisterClass *RC = TLI->getRegClassFor(
  383             ? TLI->getRegClassFor(OpVT,
  465   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
  500       TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
  570         TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());

lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp

   95           && (TLI->getRegClassFor(VT)->getID() == RCId)) {
  133           && (TLI->getRegClassFor(VT)->getID() == RCId)) {
  329           && TLI->getRegClassFor(VT)
  330           && TLI->getRegClassFor(VT)->getID() == RCId)
  340       if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT)
  341           && TLI->getRegClassFor(VT)->getID() == RCId)
  478         const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
  489         const TargetRegisterClass *RC = TLI->getRegClassFor(VT);

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 6699     const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
 8267           if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) {
 9768         RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

 1231       TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));

lib/CodeGen/SwiftErrorValueTracking.cpp

   36     const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
   58   const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
  126   auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
  241       auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));

lib/Target/AArch64/AArch64FastISel.cpp

  414     return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
  427     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
  447   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
  562   return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
 2945   unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
 3178     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
 3639     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
 3813       ResultReg1 = createResultReg(TLI.getRegClassFor(VT));

lib/Target/AArch64/AArch64ISelLowering.cpp

 3355             MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));

lib/Target/AMDGPU/SIISelLowering.cpp

10938   const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false);

lib/Target/ARM/ARMFastISel.cpp

  401   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
  411   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
  437     unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
  453   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
  517   ResultReg = createResultReg(TLI.getRegClassFor(VT));
  610         unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
  624     unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
  675     const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
  981         RC = TLI.getRegClassFor(VT);
  993       RC = TLI.getRegClassFor(VT);
 1010     unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
 1114         unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
 1575   unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
 1602   unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
 1828   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
 2054       const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
 2074       const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
 2978   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
 2990     unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));

lib/Target/ARM/ARMISelLowering.cpp

 1704   return TargetLowering::getRegClassFor(VT);

lib/Target/BPF/BPFISelLowering.cpp

  567   const TargetRegisterClass *RC = getRegClassFor(MVT::i64);

lib/Target/Hexagon/HexagonISelLowering.cpp

  738       const TargetRegisterClass *RC = getRegClassFor(RegVT);
  987   unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));

lib/Target/Lanai/LanaiISelLowering.cpp

  516       Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
 1071   unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));

lib/Target/MSP430/MSP430ISelLowering.cpp

  696             getRegClassFor(MVT::i16));

lib/Target/Mips/MipsFastISel.cpp

 1300     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));

lib/Target/Mips/MipsISelLowering.cpp

 1556   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
 1575   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
 1578     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
 1732   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
 1784   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
 1787     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
 2410   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
 3525       const TargetRegisterClass *RC = getRegClassFor(RegVT);
 3592             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
 3930     RC = getRegClassFor(VT);
 3939     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
 3942     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
 4211   const TargetRegisterClass *RC = getRegClassFor(RegTy);
 4330   const TargetRegisterClass *RC = getRegClassFor(RegTy);

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

 1188             TLI->getRegClassFor(ViaVecTy.getSimpleVT());
 1256       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);

lib/Target/PowerPC/PPCFastISel.cpp

 1521       const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
 1526       ResultReg = createResultReg(TLI.getRegClassFor(RetVT));

lib/Target/PowerPC/PPCISelLowering.cpp

10677   const TargetRegisterClass *PtrRC = getRegClassFor(PVT);

lib/Target/RISCV/RISCVISelLowering.cpp

  717   Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));

lib/Target/Sparc/SparcISelLowering.cpp

  601                                    getRegClassFor(VA.getLocVT()));
 2673     unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  928         MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));

lib/Target/X86/X86FastISel.cpp

  467   const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 2024   const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
 2199   const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
 2351   const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
 2379       const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
 2449   const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT);
 2509     return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64));
 2523     return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32));
 2625     const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16);
 2837     const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 2921         ResultReg = createResultReg(TLI.getRegClassFor(VT));
 2954                                  TLI.getRegClassFor(VT), RHSReg, RHSIsKill);
 2964         ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg,
 2968                                     TLI.getRegClassFor(VT), LHSReg, LHSIsKill,
 3047     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
 3132     const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 3731   return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
 3789   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
 3826     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
 3884   const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL));
 3918   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));

lib/Target/X86/X86ISelLowering.cpp

  604     if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
  614     if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
 3328         Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
 3477       FR.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(FR.VT));
22244     const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
29295   const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
29296   const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
30050       getRegClassFor(getPointerTy(MF->getDataLayout()));
30436   const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
30540     const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
30637   const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
31378     const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);