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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/AArch64/AArch64ISelLowering.cpp 134 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
135 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
138 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
139 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
140 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
141 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
145 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
146 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
167 addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass);
168 addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass);
169 addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass);
170 addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass);
173 addRegisterClass(MVT::nxv16i8, &AArch64::ZPRRegClass);
174 addRegisterClass(MVT::nxv8i16, &AArch64::ZPRRegClass);
175 addRegisterClass(MVT::nxv4i32, &AArch64::ZPRRegClass);
176 addRegisterClass(MVT::nxv2i64, &AArch64::ZPRRegClass);
178 addRegisterClass(MVT::nxv2f16, &AArch64::ZPRRegClass);
179 addRegisterClass(MVT::nxv4f16, &AArch64::ZPRRegClass);
180 addRegisterClass(MVT::nxv8f16, &AArch64::ZPRRegClass);
181 addRegisterClass(MVT::nxv1f32, &AArch64::ZPRRegClass);
182 addRegisterClass(MVT::nxv2f32, &AArch64::ZPRRegClass);
183 addRegisterClass(MVT::nxv4f32, &AArch64::ZPRRegClass);
184 addRegisterClass(MVT::nxv1f64, &AArch64::ZPRRegClass);
185 addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass);
897 addRegisterClass(VT, &AArch64::FPR64RegClass);
902 addRegisterClass(VT, &AArch64::FPR128RegClass);
lib/Target/AMDGPU/R600ISelLowering.cpp 58 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
59 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
60 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
61 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass);
62 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass);
63 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass);
lib/Target/AMDGPU/SIISelLowering.cpp 117 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
118 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
120 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
121 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
123 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
124 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
125 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
127 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
128 addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
130 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
131 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
133 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
134 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
136 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
137 addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
139 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
140 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
142 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
143 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
146 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
147 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
150 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
151 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
152 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
153 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
157 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
158 addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
lib/Target/ARC/ARCISelLowering.cpp 76 addRegisterClass(MVT::i32, &ARC::GPR32RegClass);
lib/Target/ARM/ARMISelLowering.cpp 215 addRegisterClass(VT, &ARM::DPRRegClass);
220 addRegisterClass(VT, &ARM::DPairRegClass);
248 addRegisterClass(VT, &ARM::MQPRRegClass);
304 addRegisterClass(VT, &ARM::MQPRRegClass);
353 addRegisterClass(VT, &ARM::MQPRRegClass);
388 addRegisterClass(VT, &ARM::VCCRRegClass);
687 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
689 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
693 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
694 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
702 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
lib/Target/AVR/AVRISelLowering.cpp 38 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
39 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
lib/Target/BPF/BPFISelLowering.cpp 62 addRegisterClass(MVT::i64, &BPF::GPRRegClass);
64 addRegisterClass(MVT::i32, &BPF::GPR32RegClass);
lib/Target/Hexagon/HexagonISelLowering.cpp 1265 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1266 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1267 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1268 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1269 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1270 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1271 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1272 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1273 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1274 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1275 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1277 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1278 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 25 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
26 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
27 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
28 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
29 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
30 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
39 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass);
40 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
41 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
42 addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);
44 addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);
45 addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);
46 addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);
47 addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass);
48 addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
49 addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass);
50 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
51 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
52 addRegisterClass(MVT::v128i1, &Hexagon::HvxQRRegClass);
53 addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass);
lib/Target/Lanai/LanaiISelLowering.cpp 77 addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
lib/Target/MSP430/MSP430ISelLowering.cpp 45 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
46 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
lib/Target/Mips/Mips16ISelLowering.cpp 125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
lib/Target/Mips/MipsSEISelLowering.cpp 67 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
70 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
88 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
126 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
171 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
176 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
178 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
318 addRegisterClass(Ty, RC);
372 addRegisterClass(Ty, RC);
lib/Target/NVPTX/NVPTXISelLowering.cpp 375 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
376 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
377 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
378 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
379 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
380 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
381 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass);
382 addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass);
lib/Target/PowerPC/PPCISelLowering.cpp 145 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
148 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
149 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
151 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
152 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
227 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
537 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
712 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
713 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
714 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
715 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
792 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
794 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
796 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
797 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
798 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
862 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
866 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
867 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
882 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
979 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
1024 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
1048 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
lib/Target/RISCV/RISCVISelLowering.cpp 68 addRegisterClass(XLenVT, &RISCV::GPRRegClass);
71 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
73 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
lib/Target/Sparc/SparcISelLowering.cpp 1422 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1424 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1425 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1426 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1429 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1433 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
lib/Target/SystemZ/SystemZISelLowering.cpp 82 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
84 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
85 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
87 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
88 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
90 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
91 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
94 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass);
96 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
99 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
100 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
101 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
102 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
103 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
104 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 54 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
55 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
56 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
57 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
59 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
60 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
61 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
62 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
65 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
66 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
lib/Target/X86/X86ISelLowering.cpp 178 addRegisterClass(MVT::i8, &X86::GR8RegClass);
179 addRegisterClass(MVT::i16, &X86::GR16RegClass);
180 addRegisterClass(MVT::i32, &X86::GR32RegClass);
182 addRegisterClass(MVT::i64, &X86::GR64RegClass);
518 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
520 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
629 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
666 addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
807 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
812 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
832 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
837 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
839 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
841 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
843 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
1094 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1096 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1098 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1100 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1102 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1104 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1292 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1293 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1294 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1295 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1296 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1358 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1359 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1360 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1361 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1591 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1592 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1630 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1631 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
lib/Target/XCore/XCoreISelLowering.cpp 77 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);