reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/BasicTTIImpl.h

  242     AM.BaseOffs = BaseOffset;
  268     AM.BaseOffs = BaseOffset;

lib/CodeGen/CodeGenPrepare.cpp

 2121     if (BaseOffs != other.BaseOffs)
 2121     if (BaseOffs != other.BaseOffs)
 2143     return !BaseOffs && !Scale && !(BaseGV && BaseReg);
 2157       return ConstantInt::get(IntPtrTy, BaseOffs);
 2194       BaseOffs = 0;
 2222   if (BaseOffs) {
 2224        << BaseOffs;
 3518     TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale;
 4164       AddrMode.BaseOffs += ConstantOffset;
 4194       AddrMode.BaseOffs -= ConstantOffset;
 4203     AddrMode.BaseOffs += ConstantOffset;
 4230       AddrMode.BaseOffs += ConstantOffset;
 4313     AddrMode.BaseOffs += CI->getSExtValue();
 4316     AddrMode.BaseOffs -= CI->getSExtValue();
 4839         !AddrMode.BaseReg && !AddrMode.Scale && !AddrMode.BaseOffs) {
 4883       if (AddrMode.BaseOffs) {
 4884         Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs);
 4988     if (AddrMode.BaseOffs) {
 4989       Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs);
 5314         AddrMode.BaseOffs = Offset - BaseOffset;

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  919       AM.BaseOffs = C2APIntVal.getSExtValue();
  927       AM.BaseOffs = CombinedValue;
13476       AM.BaseOffs = Offset->getSExtValue();
13485       AM.BaseOffs = -Offset->getSExtValue();

lib/CodeGen/TargetLoweringBase.cpp

 1735   if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
 1735   if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
 1747     if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
 1752     if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.

lib/Target/AArch64/AArch64ISelLowering.cpp

 9132   if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
 9146     int64_t Offset = AM.BaseOffs;

lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

  243         auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL);

lib/Target/AMDGPU/SIISelLowering.cpp

 1069     return AM.BaseOffs == 0 && AM.Scale == 0;
 1080     return isUInt<11>(AM.BaseOffs) && AM.Scale == 0;
 1083   return isUInt<12>(AM.BaseOffs) && AM.Scale == 0;
 1088     return isInt<13>(AM.BaseOffs) && AM.Scale == 0;
 1116   if (!isUInt<12>(AM.BaseOffs))
 1157     if (AM.BaseOffs % 4 != 0)
 1169       if (!isUInt<8>(AM.BaseOffs / 4))
 1174       if (!isUInt<32>(AM.BaseOffs / 4))
 1178       if (!isUInt<20>(AM.BaseOffs))
 1199     if (!isUInt<16>(AM.BaseOffs))
 8073   AM.BaseOffs = Offset.getSExtValue();

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

 1623     AM.BaseOffs = Dist;
 1648       AM.BaseOffs = P.second - AnchorAddr.Offset;

lib/Target/ARM/ARMISelLowering.cpp

15034   if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
15046     if (AM.BaseOffs)

lib/Target/AVR/AVRISelLowering.cpp

  747   int64_t Offs = AM.BaseOffs;

lib/Target/Hexagon/HexagonISelLowering.cpp

 3073     if ((AM.BaseOffs % A) != 0)
 3076     if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))

lib/Target/NVPTX/NVPTXISelLowering.cpp

 4229     return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;

lib/Target/PowerPC/PPCISelLowering.cpp

14472   if (Ty->isVectorTy() && AM.BaseOffs != 0)
14476   if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
14476   if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
14488     if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
14493     if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.

lib/Target/RISCV/RISCVISelLowering.cpp

  261   if (!isInt<12>(AM.BaseOffs))

lib/Target/SystemZ/SystemZISelLowering.cpp

  913   if (!isInt<20>(AM.BaseOffs))
  920   if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs))

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  519   if (AM.BaseOffs < 0)

lib/Target/X86/X86ISelLowering.cpp

28909   if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
28926         Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1))

lib/Target/XCore/XCoreISelLowering.cpp

 1888     return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
 1888     return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
 1893                  AM.BaseOffs%4 == 0;
 1900       return isImmUs(AM.BaseOffs);
 1903     return AM.Scale == 1 && AM.BaseOffs == 0;
 1908       return isImmUs2(AM.BaseOffs);
 1911     return AM.Scale == 2 && AM.BaseOffs == 0;
 1915       return isImmUs4(AM.BaseOffs);
 1918     return AM.Scale == 4 && AM.BaseOffs == 0;