|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/TargetLowering.h 2117 AddPromotedToType(Opc, OrigVT, DestVT);
lib/CodeGen/TargetLoweringBase.cpp 616 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT);
lib/Target/AArch64/AArch64ISelLowering.cpp 427 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
428 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
429 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
430 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
431 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
432 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
83 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32);
86 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
89 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
92 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32);
95 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
98 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
101 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
104 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
171 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
174 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
177 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
180 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
183 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32);
186 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
189 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
192 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32);
195 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
198 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
201 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
204 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
439 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
442 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
445 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
448 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);
lib/Target/AMDGPU/SIISelLowering.cpp 200 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
211 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
283 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
286 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
289 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
292 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
442 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
470 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
472 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
484 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
486 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
540 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
542 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
545 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
547 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
550 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
552 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
554 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
557 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
559 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
562 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
564 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
657 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
659 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
lib/Target/ARM/ARMISelLowering.cpp 154 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
157 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
193 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
195 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
197 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
lib/Target/Hexagon/HexagonISelLowering.cpp 1460 AddPromotedToType(ISD::SELECT, VT, VT32);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 66 AddPromotedToType(Opc, FromTy, ToTy);
lib/Target/Mips/MipsISelLowering.cpp 344 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
lib/Target/PowerPC/PPCISelLowering.cpp 203 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
206 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
437 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
439 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
441 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
443 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
604 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
608 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
610 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
612 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
614 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
616 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
619 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
621 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
828 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
830 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);