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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc79510 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
gen/lib/Target/X86/X86GenDAGISel.inc253979 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
include/llvm/CodeGen/SelectionDAG.h 350 SDNodeT *newSDNode(ArgTypes &&... Args) {
351 return new (NodeAllocator.template Allocate<SDNodeT>())
352 SDNodeT(std::forward<ArgTypes>(Args)...);
include/llvm/Support/Casting.h 58 return To::classof(&Val);
92 return isa_impl<To, From>::doit(*Val);
106 return isa_impl<To, From>::doit(*Val);
122 return isa_impl_wrap<To, SimpleFrom,
132 return isa_impl_cl<To,FromTy>::doit(Val);
142 return isa_impl_wrap<X, const Y,
172 using ret_type = To *; // Pointer arg case, return Ty*
176 using ret_type = const To *; // Constant pointer arg case, return const Ty*
198 using ret_type = typename cast_retty<To, SimpleFrom>::ret_type;
204 using ret_type = typename cast_retty_impl<To,FromTy>::ret_type;
210 To, From, typename simplify_type<From>::SimpleType>::ret_type;
218 static typename cast_retty<To, From>::ret_type doit(From &Val) {
219 return cast_convert_val<To, SimpleFrom,
227 static typename cast_retty<To, FromTy>::ret_type doit(const FromTy &Val) {
228 typename cast_retty<To, FromTy>::ret_type Res2
248 typename cast_retty<X, const Y>::ret_type>::type
252 X, const Y, typename simplify_type<const Y>::SimpleType>::doit(Val);
256 inline typename cast_retty<X, Y>::ret_type cast(Y &Val) {
258 return cast_convert_val<X, Y,
263 inline typename cast_retty<X, Y *>::ret_type cast(Y *Val) {
265 return cast_convert_val<X, Y*,
331 typename cast_retty<X, const Y>::ret_type>::type
333 return isa<X>(Val) ? cast<X>(Val) : nullptr;
333 return isa<X>(Val) ? cast<X>(Val) : nullptr;
337 LLVM_NODISCARD inline typename cast_retty<X, Y>::ret_type dyn_cast(Y &Val) {
338 return isa<X>(Val) ? cast<X>(Val) : nullptr;
338 return isa<X>(Val) ? cast<X>(Val) : nullptr;
342 LLVM_NODISCARD inline typename cast_retty<X, Y *>::ret_type dyn_cast(Y *Val) {
343 return isa<X>(Val) ? cast<X>(Val) : nullptr;
343 return isa<X>(Val) ? cast<X>(Val) : nullptr;
366 LLVM_NODISCARD inline typename cast_retty<X, Y *>::ret_type
368 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
368 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
include/llvm/Support/Recycler.h 83 SubClass *Allocate(AllocatorType &Allocator) {
84 static_assert(alignof(SubClass) <= Align,
86 static_assert(sizeof(SubClass) <= Size,
93 T *Allocate(AllocatorType &Allocator) {
include/llvm/Support/RecyclingAllocator.h 43 SubClass *Allocate() { return Base.template Allocate<SubClass>(Allocator); }
43 SubClass *Allocate() { return Base.template Allocate<SubClass>(Allocator); }
lib/CodeGen/SelectionDAG/DAGCombiner.cpp13565 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
13783 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
221 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
231 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
375 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
375 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
486 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
504 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
504 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
648 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
648 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
947 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
960 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
960 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
994 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1005 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1005 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1018 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1089 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1101 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 500 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 324 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1380 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1421 unsigned Reg = cast<RegisterSDNode>(OptionalDef)->getReg();
2364 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2385 cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
2956 cast<RegisterSDNode>(N->getOperand(1))->getReg()))
3003 cast<RegisterSDNode>(N->getOperand(1))->getReg()))
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 117 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
123 cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
658 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h 68 if (isa<RegisterSDNode>(Node)) return true;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 504 ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
1760 auto *N = newSDNode<RegisterSDNode>(RegNo, VT);
1760 auto *N = newSDNode<RegisterSDNode>(RegNo, VT);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 5397 Regs.emplace_back(cast<RegisterSDNode>(Op)->getReg(),
9872 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
9884 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 620 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
620 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 761 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
lib/CodeGen/SelectionDAG/TargetLowering.cpp 92 unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 549 unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
688 if (isa<RegisterSDNode>(N->getOperand(i))) {
lib/Target/AMDGPU/R600ISelLowering.cpp 2136 if (RegisterSDNode *Reg =
2137 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
lib/Target/AMDGPU/SIISelLowering.cpp10250 RegisterSDNode *DestReg = cast<RegisterSDNode>(Node->getOperand(1));
10250 RegisterSDNode *DestReg = cast<RegisterSDNode>(Node->getOperand(1));
10831 const RegisterSDNode *R = cast<RegisterSDNode>(N->getOperand(1));
10831 const RegisterSDNode *R = cast<RegisterSDNode>(N->getOperand(1));
lib/Target/ARM/ARMISelDAGToDAG.cpp 2947 cast<RegisterSDNode>(Ptr.getOperand(1))->getReg() == ARM::SP &&
4709 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
4710 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
lib/Target/ARM/ARMISelLowering.cpp 2514 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
lib/Target/AVR/AVRISelDAGToDAG.cpp 215 const RegisterSDNode *RegNode = dyn_cast<RegisterSDNode>(Op);
215 const RegisterSDNode *RegNode = dyn_cast<RegisterSDNode>(Op);
251 RegisterSDNode *RegNode =
252 cast<RegisterSDNode>(CopyFromRegOp->getOperand(1));
335 const RegisterSDNode *RN = dyn_cast<RegisterSDNode>(BasePtr.getOperand(0));
335 const RegisterSDNode *RN = dyn_cast<RegisterSDNode>(BasePtr.getOperand(0));
lib/Target/Hexagon/HexagonISelLowering.cpp 606 unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
lib/Target/PowerPC/PPCISelLowering.cpp 2590 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
lib/Target/Sparc/SparcISelDAGToDAG.cpp 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
lib/Target/Sparc/SparcISelLowering.cpp 1309 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1309 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1715 cast<RegisterSDNode>(CCUser->getOperand(1))->getReg() == SystemZ::CC) {
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 1032 unsigned Reg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
lib/Target/X86/X86ISelDAGToDAG.cpp 96 if (RegisterSDNode *RegNode =
97 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
390 RegisterSDNode *RegNode;
392 (RegNode = dyn_cast_or_null<RegisterSDNode>(
2403 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
2403 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
2414 RN = dyn_cast<RegisterSDNode>(Index);
2668 cast<RegisterSDNode>(UI->getOperand(1))->getReg() != X86::EFLAGS)
2704 cast<RegisterSDNode>(UI->getOperand(1))->getReg() != X86::EFLAGS)
2763 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() != X86::EFLAGS)
lib/Target/X86/X86ISelLowering.cpp 4234 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();