reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
270 if (RegSet.insert(P->getReg()).second) 857 unsigned AntiDepReg = Edge->getReg(); 897 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 898 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) { 912 (P->getReg() == AntiDepReg)) { 933 unsigned R = S.getReg();lib/CodeGen/CriticalAntiDepBreaker.cpp
560 AntiDepReg = Edge->getReg(); 581 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 582 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {lib/CodeGen/MachinePipeliner.cpp
1131 unsigned Reg = D.getReg(); 2651 if (Register::isPhysicalRegister(SI.getReg()))lib/CodeGen/MachineScheduler.cpp
1771 if (Succ.getKind() != SDep::Data || Succ.getReg() != LocalReg) 1786 if (Pred.getKind() != SDep::Anti || Pred.getReg() != GlobalReg) 3263 !Register::isPhysicalRegister(Dep.getReg()))lib/CodeGen/ScheduleDAG.cpp
87 dbgs() << " Reg=" << printReg(getReg(), TRI);
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp169 if (!LiveRegDefs[Pred.getReg()]) { 171 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); 172 LiveRegCycles[Pred.getReg()] = CurCycle; 194 if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) { 196 assert(LiveRegDefs[Succ.getReg()] == SU && 199 LiveRegDefs[Succ.getReg()] = nullptr; 200 LiveRegCycles[Succ.getReg()] = 0; 476 CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs,lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
563 SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; 566 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); 567 if (!LiveRegGens[Pred.getReg()]) { 569 LiveRegGens[Pred.getReg()] = SU; 772 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { 775 LiveRegDefs[Succ.getReg()] = nullptr; 776 LiveRegGens[Succ.getReg()] = nullptr; 777 releaseInterferences(Succ.getReg()); 841 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ 843 assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() && 846 LiveRegDefs[Pred.getReg()] = nullptr; 847 LiveRegGens[Pred.getReg()] = nullptr; 848 releaseInterferences(Pred.getReg()); 888 auto Reg = Succ.getReg(); 901 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && 1356 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) 1357 CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(), 2854 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && 2863 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) &&lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
801 if (II->getReg()) { 802 Reg = II->getReg(); 810 assert(I->getReg() && "Unknown physical register!"); 816 .addReg(I->getReg());lib/Target/Hexagon/HexagonSubtarget.cpp
134 if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF) 423 unsigned DepR = I.getReg();lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
527 (PI.getKind() != SDep::Data || PI.getReg() != Reg)) 930 Dep.getReg() == DepReg) 998 Hexagon::PredRegsRegClass.contains(Dep.getReg())) { 1004 if (restrictingDepExistInPacket(*I, Dep.getReg())) 1421 DepReg = SUJ->Succs[i].getReg(); 1428 if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))