reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/ScheduleDAG.h
  124       : Dep(S, Order), Contents(), Latency(0) {
  169       return getKind() == Order && (Contents.OrdKind == MayAliasMem
  175       return getKind() == Order && Contents.OrdKind == Barrier;
  187       return getKind() == Order && Contents.OrdKind == MustAliasMem;
  195       return getKind() == Order && Contents.OrdKind >= Weak;
  201       return getKind() == Order && Contents.OrdKind == Artificial;
  207       return getKind() == Order && Contents.OrdKind == Cluster;
  473     case Order:
lib/CodeGen/MachinePipeliner.cpp
  613       if (SI.getKind() == SDep::Order) {
  822       if (PMI->isPHI() && PI.getKind() == SDep::Order) {
  882       if (P.getSUnit() == &I && P.getKind() == SDep::Order)
 1178       if (PI.getKind() == SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) {
 2206   if ((Dep.getKind() != SDep::Order && Dep.getKind() != SDep::Output) ||
 2354       if (PI.getKind() == SDep::Order || Dep.getKind() == SDep::Output)
 2377       if (SI.getKind() == SDep::Order || Dep.getKind() == SDep::Output)
 2529       if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) {
 2546       if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) {
lib/CodeGen/ScheduleDAG.cpp
   80   case Order:  dbgs() << "Ord "; break;
   93   case Order:
lib/Target/Hexagon/HexagonSubtarget.cpp
  153       if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
  163           if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
 1486         DepType == SDep::Order)
 1506     if (DepType == SDep::Order) {