reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/MIRParser/MIParser.cpp

 1293     Flags |= RegState::ImplicitDefine;

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  902       MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |

lib/Target/AMDGPU/SIFrameLowering.cpp

  555         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
  577       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
  599       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
  622           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
  641           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
  652         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
  656         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
  662       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
  666       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);

lib/Target/AMDGPU/SIISelLowering.cpp

 3527           .addReg(Dst, RegState::ImplicitDefine)
 3561         .addReg(Dst, RegState::ImplicitDefine)
 3804     MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)

lib/Target/AMDGPU/SIInstrInfo.cpp

 1491             .addReg(VecReg, RegState::ImplicitDefine)

lib/Target/AMDGPU/SILowerControlFlow.cpp

  221     .addReg(Exec, RegState::ImplicitDefine);

lib/Target/AMDGPU/SIRegisterInfo.cpp

  909         MIB.addReg(SuperReg, RegState::ImplicitDefine);
  939         MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);

lib/Target/ARM/ARMBaseInstrInfo.cpp

 1343         MIB.addReg(DestReg, RegState::ImplicitDefine);
 1389           MIB.addReg(DestReg, RegState::ImplicitDefine);
 1413           MIB.addReg(DestReg, RegState::ImplicitDefine);
 1433         MIB.addReg(DestReg, RegState::ImplicitDefine);

lib/Target/ARM/ARMExpandPseudoInsts.cpp

  569   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
  737     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
 1610       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));

lib/Target/ARM/ARMFrameLowering.cpp

 1379         .addReg(SupReg, RegState::ImplicitDefine)
 1396         .addReg(SupReg, RegState::ImplicitDefine)

lib/Target/ARM/ARMISelLowering.cpp

 9860           MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  951       MIB.addReg(ImpDef, RegState::ImplicitDefine);

lib/Target/ARM/Thumb2InstrInfo.cpp

  214       MIB.addReg(DestReg, RegState::ImplicitDefine);

lib/Target/Mips/MipsFastISel.cpp

 2143       .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
 2144       .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

   56       IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;

lib/Target/Mips/MipsSEInstrInfo.cpp

  134         .addReg(DestReg, RegState::ImplicitDefine);

lib/Target/PowerPC/PPCInstrInfo.cpp

 2312         .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);

lib/Target/SystemZ/SystemZElimCompare.cpp

  241     MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
  573                            RegState::ImplicitDefine | RegState::Dead);

lib/Target/SystemZ/SystemZFrameLowering.cpp

  276         MIB.addReg(Reg, RegState::ImplicitDefine);

lib/Target/SystemZ/SystemZInstrInfo.cpp

  223     .addReg(Reg64, RegState::ImplicitDefine);

lib/Target/SystemZ/SystemZShortenInst.cpp

  147       .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);

lib/Target/X86/X86ISelLowering.cpp

30098       .addReg(X86::RAX, RegState::ImplicitDefine);
30106       .addReg(X86::EAX, RegState::ImplicitDefine);
30114       .addReg(X86::EAX, RegState::ImplicitDefine);
30255     MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
30267     MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
30279     MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
31144           MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);

lib/Target/X86/X86InstrInfo.cpp

 4112     MIB.addReg(SrcReg, RegState::ImplicitDefine);
 4141       MIB.addReg(SrcReg, RegState::ImplicitDefine);
 4216     MIB.addReg(Reg, RegState::ImplicitDefine);
 4589         .addReg(Reg, RegState::ImplicitDefine);
 4598         .addReg(Reg, RegState::ImplicitDefine);