reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1097 return !LiveInRegUnits.available(Reg); 1150 if (!UsedRegUnits.available(SrcReg)) { 1192 if (!ModifiedRegUnits.available(Reg) || !UsedRegUnits.available(Reg)) { 1192 if (!ModifiedRegUnits.available(Reg) || !UsedRegUnits.available(Reg)) { 1203 if (!ModifiedRegUnits.available(Reg)) {lib/CodeGen/RegisterScavenging.cpp
284 return !LiveUnits.available(Reg); 399 if (!MRI.isReserved(Reg) && Used.available(Reg) && 400 LiveOut.available(Reg)) 414 if (Survivor == 0 || !Used.available(Survivor)) { 417 if (!MRI.isReserved(Reg) && Used.available(Reg)) {lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
521 if (!Units.available(Reg))
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 751 if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))
lib/Target/AArch64/AArch64InstrInfo.cpp5032 C.LRU.available(Reg) && C.UsedInSequence.available(Reg)) 5032 C.LRU.available(Reg) && C.UsedInSequence.available(Reg)) 5078 return (!LRU.available(AArch64::W16) || !LRU.available(AArch64::W17) || 5078 return (!LRU.available(AArch64::W16) || !LRU.available(AArch64::W17) || 5079 !LRU.available(AArch64::NZCV)); 5197 if (C.LRU.available(AArch64::LR)) { 5213 else if (C.UsedInSequence.available(AArch64::SP)) { 5317 bool W16AvailableInBlock = LRU.available(AArch64::W16); 5318 bool W17AvailableInBlock = LRU.available(AArch64::W17); 5319 bool NZCVAvailableInBlock = LRU.available(AArch64::NZCV); 5331 if (W16AvailableInBlock && !LRU.available(AArch64::W16)) 5333 if (W17AvailableInBlock && !LRU.available(AArch64::W17)) 5335 if (NZCVAvailableInBlock && !LRU.available(AArch64::NZCV)) 5356 Reg != AArch64::X16 && Reg != AArch64::X17 && LRU.available(Reg)) { 5365 if (!CanSaveLR && !LRU.available(AArch64::LR))lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
1138 ModifiedRegUnits.available(getLdStRegOp(MI).getReg())) { 1151 if (!ModifiedRegUnits.available(BaseReg)) 1328 if (ModifiedRegUnits.available(getLdStRegOp(MI).getReg()) && 1330 !UsedRegUnits.available(getLdStRegOp(MI).getReg())) && 1340 if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg()) && 1342 !UsedRegUnits.available(getLdStRegOp(FirstMI).getReg())) && 1362 if (!ModifiedRegUnits.available(BaseReg)) 1540 if (!ModifiedRegUnits.available(BaseReg) || 1541 !UsedRegUnits.available(BaseReg)) 1595 if (!ModifiedRegUnits.available(BaseReg) || 1596 !UsedRegUnits.available(BaseReg))lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
194 if (PredI.getOperand(2).isImm() && DomBBClobberedRegs.available(SrcReg) && 214 if (!DomBBClobberedRegs.available(DstReg)) 258 if (!DomBBClobberedRegs.available(DstReg)) 327 if (!OptBBClobberedRegs.available(KnownReg.Reg)) 332 OptBBClobberedRegs.available(CopyDstReg)) { 341 OptBBClobberedRegs.available(CopySrcReg)) { 358 return !OptBBClobberedRegs.available(KnownReg.Reg);