reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

43290 /*108326*/  /*SwitchOpcode*/ 68|128,4/*580*/, TARGET_VAL(ISD::VECTOR_SHUFFLE),// ->108910

include/llvm/CodeGen/SelectionDAGNodes.h

 1524       : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
 1569     return N->getOpcode() == ISD::VECTOR_SHUFFLE;

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1595   case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
 4367   if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
11157       N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() &&
16503   if (Vec.getOpcode() == ISD::VECTOR_SHUFFLE && Vec.hasOneUse() &&
16893   if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) {
16927         TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) {
17216             !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1))
17374   if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
19016     if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
19067   if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
19068       N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
19091   if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) &&

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 2954   case ISD::VECTOR_SHUFFLE: {
 4306   case ISD::VECTOR_SHUFFLE: {

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

   95   case ISD::VECTOR_SHUFFLE:

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

   65   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
  871   case ISD::VECTOR_SHUFFLE:
 2722   case ISD::VECTOR_SHUFFLE:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  616   case ISD::VECTOR_SHUFFLE: {
 1717   AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops);
 2271   case ISD::VECTOR_SHUFFLE: {
 2356   case ISD::VECTOR_SHUFFLE: {
 2491   case ISD::VECTOR_SHUFFLE: {
 3460   case ISD::VECTOR_SHUFFLE: {
 5504   case ISD::VECTOR_SHUFFLE:

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  282   case ISD::VECTOR_SHUFFLE:             return "vector_shuffle";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

  713   case ISD::VECTOR_SHUFFLE: {
  948   case ISD::VECTOR_SHUFFLE: {
 2373   case ISD::VECTOR_SHUFFLE: {

lib/CodeGen/TargetLoweringBase.cpp

 1640   case ShuffleVector:  return ISD::VECTOR_SHUFFLE;

lib/Target/AArch64/AArch64ISelLowering.cpp

  844   setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
 3034   case ISD::VECTOR_SHUFFLE:

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  394     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
  430     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);

lib/Target/AMDGPU/SIISelLowering.cpp

  295   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
  296   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
  297   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
  298   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
  621     setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
  622     setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
 4048   case ISD::VECTOR_SHUFFLE:

lib/Target/ARM/ARMISelLowering.cpp

  177   setOperationAction(ISD::VECTOR_SHUFFLE,    VT, Custom);
  249     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
  309     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
  390     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
  923     setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
 9194   case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget);
14440   case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);

lib/Target/ARM/ARMTargetTransformInfo.cpp

  555           {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
  556           {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
  557           {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
  558           {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
  559           {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1},
  560           {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1},
  562           {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1},
  563           {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
  564           {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1},
  565           {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}};
  570               CostTableLookup(NEONDupTbl, ISD::VECTOR_SHUFFLE, LT.second))
  577           {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
  578           {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
  579           {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
  580           {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
  581           {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1},
  582           {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1},
  584           {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
  585           {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
  586           {ISD::VECTOR_SHUFFLE, MVT::v8i16, 2},
  587           {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}};
  592               CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second))
  601           {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
  602           {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
  603           {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
  604           {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
  606           {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
  607           {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
  608           {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2},
  610           {ISD::VECTOR_SHUFFLE, MVT::v8i16, 16},
  612           {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}};
  616                                               ISD::VECTOR_SHUFFLE, LT.second))
  624           {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1},
  625           {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1},
  626           {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1},
  627           {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
  628           {ISD::VECTOR_SHUFFLE, MVT::v8f16, 1}};
  632       if (const auto *Entry = CostTableLookup(MVEDupTbl, ISD::VECTOR_SHUFFLE,

lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

  902     case ISD::VECTOR_SHUFFLE:     return SelectHvxShuffle(N);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1439     ISD::CONCAT_VECTORS,        ISD::VECTOR_SHUFFLE
 1520   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8,  Custom);
 1521   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
 1522   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8,  Custom);
 2850     case ISD::VECTOR_SHUFFLE:       return LowerVECTOR_SHUFFLE(Op, DAG);

lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

   69   setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal);
   70   setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal);
  112       setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV);
  164       setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW);

lib/Target/Mips/MipsSEISelLowering.cpp

  350   setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
  466   case ISD::VECTOR_SHUFFLE:     return lowerVECTOR_SHUFFLE(Op, DAG);

lib/Target/NVPTX/NVPTXISelLowering.cpp

  390   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand);

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 4934   case ISD::VECTOR_SHUFFLE:

lib/Target/PowerPC/PPCISelLowering.cpp

  603       setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
  604       AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
  681     setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
  789       setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
  832       setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
  952     setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
 1000     setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
 1041     setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
 1133   setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
10156   case ISD::VECTOR_SHUFFLE:     return LowerVECTOR_SHUFFLE(Op, DAG);
13410   case ISD::VECTOR_SHUFFLE:
13427     if (Opcode == ISD::VECTOR_SHUFFLE && ISD::isNormalStore(N)) {

lib/Target/SystemZ/SystemZISelLowering.cpp

  331       setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
  612   setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
 4340     else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
 5020   case ISD::VECTOR_SHUFFLE:
 5281     else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) &&
 5626       Op1.getOpcode() == ISD::VECTOR_SHUFFLE &&
 6165   case ISD::VECTOR_SHUFFLE:     return combineVECTOR_SHUFFLE(N, DCI);

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  140       setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
  143         setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
 1012   case ISD::VECTOR_SHUFFLE:

lib/Target/X86/X86ISelLowering.cpp

  819     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4f32, Custom);
  910       setOperationAction(ISD::VECTOR_SHUFFLE,     VT, Custom);
  917       setOperationAction(ISD::VECTOR_SHUFFLE,     VT, Custom);
 1265       setOperationAction(ISD::VECTOR_SHUFFLE,     VT, Custom);
 1346       setOperationAction(ISD::VECTOR_SHUFFLE,   VT,  Custom);
 1499       setOperationAction(ISD::VECTOR_SHUFFLE,      VT, Custom);
 1610       setOperationAction(ISD::VECTOR_SHUFFLE,     VT, Custom);
 1655     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v32i16, Custom);
 1656     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v64i8, Custom);
 1837   setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
 6870   case ISD::VECTOR_SHUFFLE: {
 9645        isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) {
27676   case ISD::VECTOR_SHUFFLE:     return lowerVectorShuffle(Op, Subtarget, DAG);
33848   if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
33901   if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
34020     if (Opcode != ISD::VECTOR_SHUFFLE || !N->getOperand(1).isUndef())
40786     if (Op.getOpcode() == ISD::VECTOR_SHUFFLE) {
45010   case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget);