reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 3513   unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
19604       Opcode != ISD::UDIVREM && Opcode != ISD::SDIVREM) {

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3201     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
 3220     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
 4076   case ISD::UDIVREM:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 3480   if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
 3481     SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
 3507   if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
 3508     SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  369   case ISD::UDIVREM:

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  235   case ISD::UDIVREM:                    return "udivrem";

lib/Target/AArch64/AArch64ISelLowering.cpp

  326     setOperationAction(ISD::UDIVREM, VT, Expand);
  330   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
  331   setOperationAction(ISD::UDIVREM, MVT::i64, Expand);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  315     setOperationAction(ISD::UDIVREM, VT, Custom);
  385     setOperationAction(ISD::UDIVREM, VT, Expand);
 1136   case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
 1657     SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
 2001   SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);

lib/Target/AMDGPU/R600ISelLowering.cpp

  684   case ISD::UDIVREM: {

lib/Target/ARM/ARMISelLowering.cpp

 1165     setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
 1167     setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
 1170     setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
 9230   case ISD::UDIVREM:       return LowerDivRem(Op, DAG);
 9298   case ISD::UDIVREM:
15918   assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15936   assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15963   assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&

lib/Target/ARM/ARMTargetTransformInfo.cpp

  920       case ISD::UDIVREM:

lib/Target/AVR/AVRISelLowering.cpp

  155     setOperationAction(ISD::UDIVREM, VT, Custom);
  341   assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
  706   case ISD::UDIVREM:

lib/Target/BPF/BPFISelLowering.cpp

   87     setOperationAction(ISD::UDIVREM, VT, Expand);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1375         ISD::SDIVREM,   ISD::UDIVREM,   ISD::ROTL,      ISD::ROTR,
 1421     ISD::SREM,    ISD::UREM,    ISD::SDIVREM, ISD::UDIVREM,   ISD::SADDO,

lib/Target/Lanai/LanaiISelLowering.cpp

  109   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);

lib/Target/MSP430/MSP430ISelLowering.cpp

  129   setOperationAction(ISD::UDIVREM,          MVT::i8,    Promote);
  135   setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);

lib/Target/Mips/MipsISelLowering.cpp

  501   setTargetDAGCombine(ISD::UDIVREM);
 1161   case ISD::UDIVREM:

lib/Target/Mips/MipsSEISelLowering.cpp

  198     setOperationAction(ISD::UDIVREM,          MVT::i64, Custom);
  205   setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
  238     setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
  285     setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
  459   case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,

lib/Target/PowerPC/PPCISelLowering.cpp

  266   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
  268   setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
  653       setOperationAction(ISD::UDIVREM, VT, Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  128   setOperationAction(ISD::UDIVREM, XLenVT, Expand);

lib/Target/Sparc/SparcISelLowering.cpp

 1498   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
 1505     setOperationAction(ISD::UDIVREM, MVT::i64, Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  164       setOperationAction(ISD::UDIVREM, VT, Custom);
 4964   case ISD::UDIVREM:

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  113         ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,

lib/Target/X86/X86ISelDAGToDAG.cpp

 4795   case ISD::UDIVREM: {

lib/Target/X86/X86ISelLowering.cpp

  766     setOperationAction(ISD::UDIVREM, VT, Expand);
 1821     setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
25398   case ISD::UDIVREM:   isSigned = false; LC = RTLIB::UDIVREM_I128; break;
27965   case ISD::UDIVREM: {

lib/Target/X86/X86TargetTransformInfo.cpp

 3399   return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);