reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1508   case ISD::SUBCARRY:           return visitSUBCARRY(N);
 2381   if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
 2809       SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3344   case ISD::SUBCARRY: {

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  149   case ISD::SUBCARRY:    Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
 1201   case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
 1773   case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
 2138       N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
 2149       Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
 2315       CarryOp = ISD::SUBCARRY;
 3856   SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  296   case ISD::SUBCARRY:                   return "subcarry";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 7110   unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;

lib/CodeGen/TargetLoweringBase.cpp

  668     setOperationAction(ISD::SUBCARRY, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  750   case ISD::SUBCARRY:

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 1735     SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
 1737     SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
 1755     SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
 1757     SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
 1759     SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
 1775     SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
 1777     SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
 1779     SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,

lib/Target/AMDGPU/SIISelLowering.cpp

  236   setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
  703   setTargetDAGCombine(ISD::SUBCARRY);
 9543     Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
 9569   if (LHS.getOpcode() == ISD::SUBCARRY) {
 9575     return DAG.getNode(ISD::SUBCARRY, SDLoc(N), LHS->getVTList(), Args);
 9598       (LHSOpc == ISD::SUB && Opc == ISD::SUBCARRY)) {
 9945   case ISD::SUBCARRY:

lib/Target/ARM/ARMISelLowering.cpp

 1023   setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
 9210   case ISD::SUBCARRY:      return LowerADDSUBCARRY(Op, DAG);
14392     Res = DAG.getNode(ISD::SUBCARRY, dl, VTs, FalseVal, Subc, Subc.getValue(1));

lib/Target/Hexagon/HexagonISelLowering.cpp

 1347     setOperationAction(ISD::SUBCARRY, VT, Expand);
 1350   setOperationAction(ISD::SUBCARRY, MVT::i64, Custom);
 2857     case ISD::SUBCARRY:             return LowerAddSubCarry(Op, DAG);

lib/Target/SystemZ/SystemZISelLowering.cpp

  176       setOperationAction(ISD::SUBCARRY, VT, Custom);
 3487   while (Carry.getOpcode() == ISD::SUBCARRY)
 3521   case ISD::SUBCARRY:
 4972   case ISD::SUBCARRY:

lib/Target/X86/X86ISelLowering.cpp

 1796     setOperationAction(ISD::SUBCARRY, VT, Custom);
27763   case ISD::SUBCARRY:           return LowerADDSUBCARRY(Op, DAG);