|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc27973 /* 58677*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
28005 /* 58734*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
54677 /*119872*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SETCC),// ->119908
60293 /*131940*/ /*SwitchOpcode*/ 9|128,35/*4489*/, TARGET_VAL(ISD::SETCC),// ->136433
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc23969 /* 46145*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
24232 /* 46631*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
28269 /* 54622*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
28532 /* 55108*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
28976 /* 55922*/ /*SwitchOpcode*/ 53|128,28/*3637*/, TARGET_VAL(ISD::SETCC),// ->59563
30817 /* 59577*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
51493 /* 97018*/ OPC_SwitchOpcode /*2 cases */, 51|128,4/*563*/, TARGET_VAL(ISD::SETCC),// ->97586
51936 /* 97889*/ OPC_SwitchOpcode /*2 cases */, 16|128,1/*144*/, TARGET_VAL(ISD::SETCC),// ->98038
52077 /* 98153*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
52268 /* 98573*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
54490 /*102918*/ /*SwitchOpcode*/ 96|128,3/*480*/, TARGET_VAL(ISD::SETCC),// ->103402
54825 /*103531*/ /*SwitchOpcode*/ 114|128,3/*498*/, TARGET_VAL(ISD::SETCC),// ->104033
65449 /*125970*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::SETCC),// ->126053
68505 /*132676*/ OPC_SwitchOpcode /*2 cases */, 120|128,11/*1528*/, TARGET_VAL(ISD::SETCC),// ->134209
gen/lib/Target/Mips/MipsGenDAGISel.inc 1379 /* 2474*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
2975 /* 5336*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
4564 /* 8688*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
5239 /* 10096*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
14950 /* 27587*/ OPC_SwitchOpcode /*2 cases */, 84, TARGET_VAL(ISD::SETCC),// ->27675
16482 /* 30560*/ /*SwitchOpcode*/ 105|128,26/*3433*/, TARGET_VAL(ISD::SETCC),// ->33997
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc52989 /*114398*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
58744 /*124686*/ /*SwitchOpcode*/ 122|128,27|128,1/*19962*/, TARGET_VAL(ISD::SETCC),// ->144653
gen/lib/Target/PowerPC/PPCGenDAGISel.inc 3527 /* 7471*/ /*SwitchOpcode*/ 105|128,72/*9321*/, TARGET_VAL(ISD::SETCC),// ->16796
7182 /* 17237*/ /*SwitchOpcode*/ 105|128,72/*9321*/, TARGET_VAL(ISD::SETCC),// ->26562
10861 /* 27088*/ /*SwitchOpcode*/ 78|128,60/*7758*/, TARGET_VAL(ISD::SETCC),// ->34850
19270 /* 48698*/ OPC_SwitchOpcode /*4 cases */, 117|128,4/*629*/, TARGET_VAL(ISD::SETCC),// ->49332
19641 /* 49655*/ OPC_SwitchOpcode /*2 cases */, 116|128,12/*1652*/, TARGET_VAL(ISD::SETCC),// ->51312
25117 /* 60485*/ /*SwitchOpcode*/ 2|128,45/*5762*/, TARGET_VAL(ISD::SETCC),// ->66251
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 6678 /* 12306*/ /*SwitchOpcode*/ 58|128,15/*1978*/, TARGET_VAL(ISD::SETCC),// ->14288
7671 /* 14414*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 7411 /* 13765*/ /*SwitchOpcode*/ 19|128,12/*1555*/, TARGET_VAL(ISD::SETCC),// ->15324
12534 /* 24164*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
12658 /* 24378*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
12739 /* 24527*/ OPC_SwitchOpcode /*2 cases */, 69, TARGET_VAL(ISD::SETCC),// ->24600
gen/lib/Target/X86/X86GenDAGISel.inc23214 /* 47219*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
25134 /* 50979*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
25933 /* 52601*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
26553 /* 53925*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
27133 /* 55357*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
29938 /* 61540*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
30305 /* 62253*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
30703 /* 62999*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
31180 /* 64368*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
207482 /*420399*/ /*SwitchOpcode*/ 107|128,52/*6763*/, TARGET_VAL(ISD::SETCC),// ->427166
gen/lib/Target/XCore/XCoreGenDAGISel.inc 1334 /* 2205*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
1504 /* 2519*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
1730 /* 2975*/ /*SwitchOpcode*/ 3|128,2/*259*/, TARGET_VAL(ISD::SETCC),// ->3238
include/llvm/CodeGen/SelectionDAG.h 985 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 809 if (N.getOpcode() == ISD::SETCC) {
1549 case ISD::SETCC: return visitSETCC(N);
2009 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
4551 TLI.isOperationLegal(ISD::SETCC, OpVT))))
6913 case ISD::SETCC:
7305 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
8188 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() ||
8450 if (N0.getOpcode() == ISD::SETCC) {
8697 if (N0.getOpcode() == ISD::SETCC) {
8752 TLI.isOperationLegalOrCustom(ISD::SETCC, WideVT)) {
8819 } else if (SCC.getOpcode() == ISD::SETCC) {
8853 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) {
8875 return DAG.getNode(ISD::SETCC, SDLoc(N), N->getVTList(), LHS, RHS, Cond);
8988 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
9050 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
9252 VSel.getOperand(0).getOpcode() != ISD::SETCC)
9385 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC ||
9542 if (N0.getOpcode() == ISD::SETCC) {
9606 (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT))) {
9655 if (N.getOpcode() != ISD::SETCC ||
9877 if (N0.getOpcode() == ISD::SETCC) {
9894 SDValue VSetCC = DAG.getNode(ISD::SETCC, DL, VT, N0.getOperand(0),
9904 DAG.getNode(ISD::SETCC, DL, MatchingVectorType, N0.getOperand(0),
10057 if (N0.getOpcode() == ISD::SETCC) {
12283 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X &&
12851 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
12866 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
12912 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
13309 if (N1.getOpcode() == ISD::SETCC &&
13401 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
13401 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
13440 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
19682 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
19695 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
19735 if (Cmp.getOpcode() == ISD::SETCC) {
20100 (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT))) {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1026 case ISD::SETCC:
1029 Node->getOpcode() == ISD::SETCC ? 2 : 1;
3425 if (Tmp1.getOpcode() == ISD::SETCC) {
3484 if (Tmp2.getOpcode() == ISD::SETCC) {
3506 case ISD::SETCC: {
3517 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3567 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags());
4127 Node->getOpcode() == ISD::SETCC ||
4319 case ISD::SETCC: {
4328 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1,
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 851 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
1656 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1923 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 78 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
1175 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
3609 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
3718 DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp 524 else if (Cond.getOpcode() == ISD::SETCC) {
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 396 case ISD::SETCC:
794 case ISD::SETCC:
1430 Ops[i] = DAG.getNode(ISD::SETCC, dl,
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 63 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
474 if (Cond->getOpcode() == ISD::SETCC) {
567 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
622 case ISD::SETCC:
753 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
868 case ISD::SETCC:
1588 if (Mask.getOpcode() == ISD::SETCC) {
1654 if (Mask.getOpcode() == ISD::SETCC) {
1980 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
2380 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) {
2441 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) {
2639 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2640 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2720 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
3834 return (N.getOpcode() == ISD::SETCC ||
3905 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3928 if (Cond.getOpcode() == ISD::SETCC) {
3960 if (Cond->getOpcode() == ISD::SETCC) {
3964 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3965 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
4118 return DAG.getNode(ISD::SETCC, SDLoc(N),
4152 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
4566 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2788 case ISD::SETCC:
3652 case ISD::SETCC:
4921 EVT SVT = (Opcode == ISD::SETCC ? MVT::i1 : VT.getScalarType());
5479 case ISD::SETCC: {
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 271 case ISD::SETCC: return "setcc";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 394 ISD::SETCC, dl,
399 ISD::SETCC, dl,
1245 case ISD::SETCC: {
3190 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
3213 TopSetCC.getOpcode() == ISD::SETCC &&
3333 (isOperationLegal(ISD::SETCC, newVT) &&
3381 if (N0.getOpcode() == ISD::SETCC &&
3435 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
3436 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
6859 assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
lib/CodeGen/TargetLoweringBase.cpp 1630 case ICmp: return ISD::SETCC;
1631 case FCmp: return ISD::SETCC;
lib/Target/AArch64/AArch64ISelLowering.cpp 194 setOperationAction(ISD::SETCC, MVT::i32, Custom);
195 setOperationAction(ISD::SETCC, MVT::i64, Custom);
196 setOperationAction(ISD::SETCC, MVT::f16, Custom);
197 setOperationAction(ISD::SETCC, MVT::f32, Custom);
198 setOperationAction(ISD::SETCC, MVT::f64, Custom);
253 setOperationAction(ISD::SETCC, MVT::f128, Custom);
399 setOperationAction(ISD::SETCC, MVT::f16, Promote);
438 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
465 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
682 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
850 setOperationAction(ISD::SETCC, VT, Custom);
1754 if (Opcode == ISD::SETCC) {
1815 if (Opcode == ISD::SETCC) {
2974 case ISD::SETCC:
5241 if (CCVal.getOpcode() == ISD::SETCC) {
9490 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
10192 if (Op.getOpcode() == ISD::SETCC) {
11569 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
11600 if (N0.getOpcode() != ISD::SETCC)
11643 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2020 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 395 setOperationAction(ISD::SETCC, VT, Expand);
431 setOperationAction(ISD::SETCC, VT, Expand);
3548 if (Cond.getOpcode() != ISD::SETCC)
lib/Target/AMDGPU/R600ISelLowering.cpp 143 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
144 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
160 setOperationAction(ISD::SETCC, MVT::i32, Expand);
161 setOperationAction(ISD::SETCC, MVT::f32, Expand);
884 ISD::SETCC,
894 ISD::SETCC,
lib/Target/AMDGPU/SIISelLowering.cpp 208 setOperationAction(ISD::SETCC, MVT::i1, Promote);
209 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
210 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
211 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
715 setTargetDAGCombine(ISD::SETCC);
1391 if (VT == MVT::i1 && Op == ISD::SETCC)
4443 if (Intr->getOpcode() == ISD::SETCC) {
8153 case ISD::SETCC:
8292 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
8292 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
8330 if (RHS.getOpcode() == ISD::SETCC && LHS.getOpcode() == AMDGPUISD::FP_CLASS)
8333 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == AMDGPUISD::FP_CLASS &&
9951 case ISD::SETCC:
lib/Target/ARM/ARMISelLowering.cpp 162 setOperationAction(ISD::SETCC, VT, Custom);
261 setOperationAction(ISD::SETCC, VT, Custom);
316 setOperationAction(ISD::SETCC, VT, Custom);
395 setOperationAction(ISD::SETCC, VT, Custom);
776 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
1272 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1273 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1274 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1282 setOperationAction(ISD::SETCC, MVT::f16, Expand);
6195 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
9190 case ISD::SETCC: return LowerVSETCC(Op, DAG, Subtarget);
10865 if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC)
11674 case ISD::SETCC:
14052 case ISD::SETCC: {
lib/Target/AVR/AVRISelLowering.cpp 106 setOperationAction(ISD::SETCC, MVT::i8, Custom);
107 setOperationAction(ISD::SETCC, MVT::i16, Custom);
108 setOperationAction(ISD::SETCC, MVT::i32, Custom);
109 setOperationAction(ISD::SETCC, MVT::i64, Custom);
701 case ISD::SETCC:
lib/Target/BPF/BPFISelLowering.cpp 101 setOperationAction(ISD::SETCC, VT, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1315 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1316 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1317 setOperationAction(ISD::SETCC, MVT::v4i8, Custom);
1318 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1517 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
2874 case ISD::SETCC: return LowerSETCC(Op, DAG);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 156 setOperationAction(ISD::SETCC, T, Custom);
178 setOperationAction(ISD::SETCC, BoolW, Custom);
1544 case ISD::SETCC:
1574 case ISD::SETCC:
lib/Target/Lanai/LanaiISelLowering.cpp 88 setOperationAction(ISD::SETCC, MVT::i32, Custom);
192 case ISD::SETCC:
lib/Target/MSP430/MSP430ISelLowering.cpp 88 setOperationAction(ISD::SETCC, MVT::i8, Custom);
89 setOperationAction(ISD::SETCC, MVT::i16, Custom);
343 case ISD::SETCC: return LowerSETCC(Op, DAG);
lib/Target/Mips/MipsISelLowering.cpp 344 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
356 setOperationAction(ISD::SETCC, MVT::f32, Custom);
357 setOperationAction(ISD::SETCC, MVT::f64, Custom);
646 if (Op.getOpcode() != ISD::SETCC)
684 if ((SetCC.getOpcode() != ISD::SETCC) ||
1228 case ISD::SETCC: return lowerSETCC(Op, DAG);
lib/Target/Mips/MipsSEISelLowering.cpp 104 setTargetDAGCombine(ISD::SETCC);
127 setOperationAction(ISD::SETCC, MVT::f16, Promote);
246 setOperationAction(ISD::SETCC, MVT::i32, Legal);
250 setOperationAction(ISD::SETCC, MVT::f32, Legal);
255 setOperationAction(ISD::SETCC, MVT::f64, Legal);
293 setOperationAction(ISD::SETCC, MVT::i64, Legal);
361 setOperationAction(ISD::SETCC, Ty, Legal);
398 setOperationAction(ISD::SETCC, Ty, Legal);
1050 case ISD::SETCC:
lib/Target/NVPTX/NVPTXISelLowering.cpp 392 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
393 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
528 setTargetDAGCombine(ISD::SETCC);
4772 case ISD::SETCC:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 2541 else if (N->getOperand(0).getOpcode() != ISD::SETCC)
2668 if (OperandOpcode == ISD::SETCC)
3553 assert(Compare.getOpcode() == ISD::SETCC &&
3578 assert((Compare.getOpcode() == ISD::SETCC ||
3584 if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG))
4239 if (SetOrSelCC.getOpcode() != ISD::SETCC &&
4381 case ISD::SETCC:
lib/Target/PowerPC/PPCISelLowering.cpp 365 setOperationAction(ISD::SETCC, MVT::i32, Custom);
813 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
820 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1138 setTargetDAGCombine(ISD::SETCC);
10120 case ISD::SETCC: return LowerSETCC(Op, DAG);
11943 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
11975 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
12038 if (N->getOpcode() == ISD::SETCC ||
12044 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
12056 return (N->getOpcode() == ISD::SETCC ? ConvertSETCCToSubtract(N, DCI)
12088 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
12581 assert(N->getOpcode() == ISD::SETCC &&
13401 case ISD::SETCC:
15194 if (Cmp.getOpcode() != ISD::SETCC || !Cmp.hasOneUse() ||
15527 if (Cond.getOpcode() != ISD::SETCC || TrueOpnd.getOpcode() != ISD::SUB ||
lib/Target/RISCV/RISCVISelLowering.cpp 626 if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
lib/Target/Sparc/SparcISelLowering.cpp 1529 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1530 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1531 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1532 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1561 setOperationAction(ISD::SETCC, MVT::i64, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 134 setOperationAction(ISD::SETCC, VT, Custom);
375 setOperationAction(ISD::SETCC, VT, Custom);
4936 case ISD::SETCC:
5445 if (EVT == MVT::i1 && N0.hasOneUse() && N0.getOpcode() == ISD::SETCC) {
lib/Target/X86/X86ISelDAGToDAG.cpp 539 if (Opcode == X86ISD::CMPM || Opcode == ISD::SETCC ||
4483 if (N0.getOpcode() == ISD::SETCC && N0.hasOneUse() &&
4486 if (N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
5182 case ISD::SETCC: {
lib/Target/X86/X86ISelLowering.cpp 417 setOperationAction(ISD::SETCC, VT, Custom);
423 setOperationAction(ISD::SETCC, VT, Custom);
703 setOperationAction(ISD::SETCC, MVT::f128, Custom);
773 setOperationAction(ISD::SETCC, VT, Expand);
897 setOperationAction(ISD::SETCC, VT, Custom);
1171 setOperationAction(ISD::SETCC, VT, Custom);
1333 setOperationAction(ISD::SETCC, VT, Custom);
1461 setOperationAction(ISD::SETCC, VT, Custom);
1605 setOperationAction(ISD::SETCC, VT, Custom);
1682 setOperationAction(ISD::SETCC, VT, Custom);
1873 setTargetDAGCombine(ISD::SETCC);
8537 if (Cond.getOpcode() != ISD::SETCC)
20009 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
20085 UI->getOpcode() != ISD::SETCC &&
20492 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
21213 if (Cond.getOpcode() == ISD::SETCC &&
21308 if (Cond.getOpcode() == ISD::SETCC) {
21974 if (Cond.getOpcode() == ISD::SETCC) {
22109 } else if (Cond.getOpcode() == ISD::SETCC &&
22140 } else if (Cond.getOpcode() == ISD::SETCC &&
27717 case ISD::SETCC: return LowerSETCC(Op, DAG);
35180 case ISD::SETCC:
35195 case ISD::SETCC:
35479 VT.isScalarInteger() && N0.getOpcode() == ISD::SETCC &&
36181 if (Vec.getOpcode() == ISD::SETCC && VT == MVT::i1) {
36205 Vec.getOperand(0).getOpcode() == ISD::SETCC &&
36570 Cond.getOpcode() == ISD::SETCC &&
36835 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
36990 Cond.getOpcode() == ISD::SETCC && (VT == MVT::f32 || VT == MVT::f64)) {
37072 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
37090 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
37159 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
39146 if (SubVec.getOpcode() != ISD::SETCC || !TLI.isTypeLegal(SubVecVT) ||
42416 if (!Subtarget.hasAVX512() || !VT.isVector() || N0.getOpcode() != ISD::SETCC)
42882 SDValue Setcc = DAG.getNode(ISD::SETCC, DL, OpVT, LHS, RHS,
43116 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
44963 case ISD::SETCC: return combineSetCC(N, DAG, Subtarget);
lib/Target/X86/X86TargetTransformInfo.cpp 1747 { ISD::SETCC, MVT::v2i64, 2 },
1751 { ISD::SETCC, MVT::v32i16, 1 },
1752 { ISD::SETCC, MVT::v64i8, 1 },
1759 { ISD::SETCC, MVT::v8i64, 1 },
1760 { ISD::SETCC, MVT::v16i32, 1 },
1761 { ISD::SETCC, MVT::v8f64, 1 },
1762 { ISD::SETCC, MVT::v16f32, 1 },
1771 { ISD::SETCC, MVT::v4i64, 1 },
1772 { ISD::SETCC, MVT::v8i32, 1 },
1773 { ISD::SETCC, MVT::v16i16, 1 },
1774 { ISD::SETCC, MVT::v32i8, 1 },
1783 { ISD::SETCC, MVT::v4f64, 1 },
1784 { ISD::SETCC, MVT::v8f32, 1 },
1786 { ISD::SETCC, MVT::v4i64, 4 },
1787 { ISD::SETCC, MVT::v8i32, 4 },
1788 { ISD::SETCC, MVT::v16i16, 4 },
1789 { ISD::SETCC, MVT::v32i8, 4 },
1800 { ISD::SETCC, MVT::v2f64, 1 },
1801 { ISD::SETCC, MVT::v4f32, 1 },
1802 { ISD::SETCC, MVT::v2i64, 1 },
1815 { ISD::SETCC, MVT::v2f64, 2 },
1816 { ISD::SETCC, MVT::f64, 1 },
1817 { ISD::SETCC, MVT::v2i64, 8 },
1818 { ISD::SETCC, MVT::v4i32, 1 },
1819 { ISD::SETCC, MVT::v8i16, 1 },
1820 { ISD::SETCC, MVT::v16i8, 1 },
1830 { ISD::SETCC, MVT::v4f32, 2 },
1831 { ISD::SETCC, MVT::f32, 1 },