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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc21422 /* 40859*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ROTL),// ->40916
21549 /* 41086*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::ROTL),// ->41145
24880 /* 47819*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ROTL),// ->47876
25007 /* 48046*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::ROTL),// ->48105
26205 /* 50339*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ROTL),// ->50396
26823 /* 51553*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ROTL),// ->51610
26950 /* 51780*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::ROTL),// ->51839
53742 /*101512*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ROTL),// ->101569
53838 /*101684*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::ROTL),// ->101743
63696 /*122088*/ /*SwitchOpcode*/ 72|128,1/*200*/, TARGET_VAL(ISD::ROTL),// ->122292
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58608 /*124426*/ /*SwitchOpcode*/ 105, TARGET_VAL(ISD::ROTL),// ->124534
gen/lib/Target/PowerPC/PPCGenDAGISel.inc22806 /* 56291*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::ROTL),// ->56329
27631 /* 66890*/ /*SwitchOpcode*/ 87, TARGET_VAL(ISD::ROTL),// ->66980
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc18422 /* 34319*/ /*SwitchOpcode*/ 65|128,1/*193*/, TARGET_VAL(ISD::ROTL),// ->34516
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc12577 /* 24231*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ROTL),// ->24301
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1913 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc 1503 /* 3051*/ /*SwitchOpcode*/ 44|128,6/*812*/, TARGET_VAL(ISD::ROTL),// ->3867
20333 /* 41106*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTL),
20387 /* 41239*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTL),
20620 /* 41743*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTL),
20658 /* 41852*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTL),
34582 /* 71968*/ /*SwitchOpcode*/ 75|128,11/*1483*/, TARGET_VAL(ISD::ROTL),// ->73455
79689 /*167325*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::ROTL),// ->167408
84675 /*177374*/ /*SwitchOpcode*/ 78, TARGET_VAL(ISD::ROTL),// ->177455
89902 /*187538*/ /*SwitchOpcode*/ 14|128,1/*142*/, TARGET_VAL(ISD::ROTL),// ->187684
96064 /*200030*/ /*SwitchOpcode*/ 10|128,1/*138*/, TARGET_VAL(ISD::ROTL),// ->200172
102979 /*213667*/ /*SwitchOpcode*/ 14|128,1/*142*/, TARGET_VAL(ISD::ROTL),// ->213813
110203 /*228459*/ /*SwitchOpcode*/ 10|128,1/*138*/, TARGET_VAL(ISD::ROTL),// ->228601
116808 /*241481*/ /*SwitchOpcode*/ 6|128,1/*134*/, TARGET_VAL(ISD::ROTL),// ->241619
124812 /*256942*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::ROTL),// ->256989
127195 /*261520*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::ROTL),// ->261565
145929 /*298483*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTL),
147800 /*302038*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::ROTL),// ->302061
159838 /*324769*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::ROTL),// ->324816
161534 /*328003*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::ROTL),// ->328048
177539 /*359915*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::ROTL),// ->359939
178460 /*361600*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::ROTL),// ->361623
gen/lib/Target/X86/X86GenFastISel.inc13521 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
14115 case ISD::ROTL: return fastEmit_ISD_ROTL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1535 case ISD::ROTL: return visitRotate(N);
5593 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
5594 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
6143 bool HasROTL = hasOperation(ISD::ROTL, VT);
6221 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
6267 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
6272 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
7035 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0Opcode == ISD::SHL &&
7037 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT),
7260 if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) {
8000 unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1174 case ISD::ROTL:
2610 return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
3326 case ISD::ROTL:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1197 case ISD::ROTL:
3619 case ISD::ROTL:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 383 case ISD::ROTL:
811 case ISD::ROTL:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3658 case ISD::ROTL:
4706 case ISD::ROTL: return std::make_pair(C1.rotl(C2), true);
5142 case ISD::ROTL:
9157 case ISD::ROTL:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6245 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
6252 RotateOpcode = IsFSHL ? ISD::ROTR : ISD::ROTL;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 242 case ISD::ROTL: return "rotl";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2502 case ISD::ROTL:
5838 bool IsLeft = Node->getOpcode() == ISD::ROTL;
5847 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
lib/Target/AArch64/AArch64ISelLowering.cpp 308 setOperationAction(ISD::ROTL, MVT::i32, Expand);
309 setOperationAction(ISD::ROTL, MVT::i64, Expand);
311 setOperationAction(ISD::ROTL, VT, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 333 setOperationAction(ISD::ROTL, MVT::i32, Expand);
334 setOperationAction(ISD::ROTL, MVT::i64, Expand);
373 setOperationAction(ISD::ROTL, VT, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 445 setOperationAction(ISD::ROTL, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 1070 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1072 setOperationAction(ISD::ROTL, VT, Expand);
lib/Target/AVR/AVRISelLowering.cpp 91 setOperationAction(ISD::ROTL, MVT::i8, Custom);
92 setOperationAction(ISD::ROTL, MVT::i16, Expand);
297 case ISD::ROTL:
316 case ISD::ROTL:
690 case ISD::ROTL:
lib/Target/BPF/BPFISelLowering.cpp 95 setOperationAction(ISD::ROTL, VT, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1375 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1424 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1557 setOperationAction(ISD::ROTL, MVT::i32, Legal);
1558 setOperationAction(ISD::ROTL, MVT::i64, Legal);
2861 case ISD::ROTL: return LowerROTL(Op, DAG);
lib/Target/Lanai/LanaiISelLowering.cpp 120 setOperationAction(ISD::ROTL, MVT::i32, Expand);
lib/Target/MSP430/MSP430ISelLowering.cpp 77 setOperationAction(ISD::ROTL, MVT::i8, Expand);
79 setOperationAction(ISD::ROTL, MVT::i16, Expand);
lib/Target/Mips/MipsISelLowering.cpp 425 setOperationAction(ISD::ROTL, MVT::i32, Expand);
426 setOperationAction(ISD::ROTL, MVT::i64, Expand);
lib/Target/NVPTX/NVPTXISelLowering.cpp 423 setOperationAction(ISD::ROTL, MVT::i64, Legal);
425 setOperationAction(ISD::ROTL, MVT::i32, Legal);
428 setOperationAction(ISD::ROTL, MVT::i16, Expand);
430 setOperationAction(ISD::ROTL, MVT::i8, Expand);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 613 } else if (Opcode == ISD::ROTL) {
1227 case ISD::ROTL:
3659 case ISD::ROTL:
4586 N->getOperand(0).getOpcode() != ISD::ROTL) {
lib/Target/PowerPC/PPCISelLowering.cpp 659 setOperationAction(ISD::ROTL, VT, Expand);
lib/Target/RISCV/RISCVISelLowering.cpp 136 setOperationAction(ISD::ROTL, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1570 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1633 setOperationAction(ISD::ROTL , MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 829 case ISD::ROTL: {
1518 case ISD::ROTL:
lib/Target/SystemZ/SystemZISelLowering.cpp 370 setOperationAction(ISD::ROTL, VT, Expand);
3732 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 176 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
lib/Target/X86/X86ISelDAGToDAG.cpp 675 if (U0.getOpcode() == ISD::ROTL) {
681 if (U1.getOpcode() == ISD::ROTL) {
lib/Target/X86/X86ISelLowering.cpp 770 setOperationAction(ISD::ROTL, VT, Expand);
1005 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1006 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1010 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1080 setOperationAction(ISD::ROTL, VT, Custom);
1145 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1146 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1150 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1459 setOperationAction(ISD::ROTL, VT, Custom);
1552 setOperationAction(ISD::ROTL, VT, Custom);
26273 unsigned Op = (Opcode == ISD::ROTL ? X86ISD::VROTLI : X86ISD::VROTRI);
26283 assert((Opcode == ISD::ROTL) && "Only ROTL supported");
27749 case ISD::ROTL:
lib/Target/X86/X86TargetTransformInfo.cpp 2285 { ISD::ROTL, MVT::v8i64, 1 },
2286 { ISD::ROTL, MVT::v4i64, 1 },
2287 { ISD::ROTL, MVT::v2i64, 1 },
2288 { ISD::ROTL, MVT::v16i32, 1 },
2289 { ISD::ROTL, MVT::v8i32, 1 },
2290 { ISD::ROTL, MVT::v4i32, 1 },
2300 { ISD::ROTL, MVT::v4i64, 4 },
2301 { ISD::ROTL, MVT::v8i32, 4 },
2302 { ISD::ROTL, MVT::v16i16, 4 },
2303 { ISD::ROTL, MVT::v32i8, 4 },
2304 { ISD::ROTL, MVT::v2i64, 1 },
2305 { ISD::ROTL, MVT::v4i32, 1 },
2306 { ISD::ROTL, MVT::v8i16, 1 },
2307 { ISD::ROTL, MVT::v16i8, 1 },
2318 { ISD::ROTL, MVT::i64, 1 },
2323 { ISD::ROTL, MVT::i32, 1 },
2324 { ISD::ROTL, MVT::i16, 1 },
2325 { ISD::ROTL, MVT::i8, 1 },
2341 ISD = ISD::ROTL;
lib/Target/XCore/XCoreISelLowering.cpp 107 setOperationAction(ISD::ROTL , MVT::i32, Expand);