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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc101796 /*227996*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::CTTZ),// ->228038
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc63961 /*122714*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::CTTZ),// ->122763
65388 /*125832*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::CTTZ),// ->125928
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 1278 /* 2324*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::CTTZ),// ->2335
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28317 /* 68169*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::CTTZ),// ->68253
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1698 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc29137 /* 55271*/ /*SwitchOpcode*/ 55, TARGET_VAL(ISD::CTTZ),// ->55329
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18396 /* 35252*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::CTTZ),// ->35280
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 963 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc38108 /* 79775*/ /*SwitchOpcode*/ 7|128,1/*135*/, TARGET_VAL(ISD::CTTZ),// ->79914
gen/lib/Target/X86/X86GenFastISel.inc 5910 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2194 /* 3833*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::CTTZ),// ->3851
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1543 case ISD::CTTZ: return visitCTTZ(N);
3716 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
8086 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
20157 if ((Count.getOpcode() == ISD::CTTZ ||
20160 (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ, VT)))
20161 return DAG.getNode(ISD::CTTZ, DL, VT, N0);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2673 case ISD::CTTZ:
4138 case ISD::CTTZ:
4145 if (Node->getOpcode() == ISD::CTTZ) {
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 67 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
454 if (N->getOpcode() == ISD::CTTZ) {
1697 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 389 case ISD::CTTZ:
805 case ISD::CTTZ:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 78 case ISD::CTTZ:
888 case ISD::CTTZ:
2017 case ISD::CTTZ:
2891 case ISD::CTTZ:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2894 case ISD::CTTZ:
4336 case ISD::CTTZ:
4447 case ISD::CTTZ:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6206 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 387 case ISD::CTTZ: return "cttz";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6281 isOperationLegalOrCustom(ISD::CTTZ, VT)) {
6282 Result = DAG.getNode(ISD::CTTZ, dl, VT, Op);
lib/Target/AArch64/AArch64ISelLowering.cpp 770 setOperationAction(ISD::CTTZ, VT, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 322 setOperationAction(ISD::CTTZ, VT, Expand);
351 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
392 setOperationAction(ISD::CTTZ, VT, Expand);
1156 case ISD::CTTZ:
2312 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
lib/Target/AMDGPU/SIISelLowering.cpp 455 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 265 setOperationAction(ISD::CTTZ, VT, Custom);
873 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
874 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
875 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
876 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
878 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
879 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
880 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
881 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
1075 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
9187 case ISD::CTTZ:
lib/Target/AVR/AVRISelLowering.cpp 182 setOperationAction(ISD::CTTZ, VT, Expand);
lib/Target/BPF/BPFISelLowering.cpp 112 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
lib/Target/Hexagon/HexagonISelLowering.cpp 1354 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1355 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1425 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 89 setOperationAction(ISD::CTTZ, T, Custom);
145 setOperationAction(ISD::CTTZ, T, Custom);
1534 case ISD::CTTZ:
1566 case ISD::CTTZ: return LowerHvxCttz(Op, DAG);
lib/Target/Lanai/LanaiISelLowering.cpp 128 setOperationAction(ISD::CTTZ, MVT::i32, Legal);
lib/Target/MSP430/MSP430ISelLowering.cpp 100 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
101 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
lib/Target/Mips/MipsISelLowering.cpp 423 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
424 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
lib/Target/NVPTX/NVPTXISelLowering.cpp 505 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
506 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
507 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
lib/Target/PowerPC/PPCISelLowering.cpp 332 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
333 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
335 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
336 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
598 setOperationAction(ISD::CTTZ, VT, Legal);
600 setOperationAction(ISD::CTTZ, VT, Expand);
lib/Target/RISCV/RISCVISelLowering.cpp 139 setOperationAction(ISD::CTTZ, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1567 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1631 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 194 setOperationAction(ISD::CTTZ, VT, Expand);
352 setOperationAction(ISD::CTTZ, VT, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 175 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
lib/Target/X86/X86ISelLowering.cpp 339 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
342 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
343 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
347 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
768 setOperationAction(ISD::CTTZ, VT, Expand);
24809 assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ &&
27744 case ISD::CTTZ:
37782 Add.getOperand(0).getOpcode() == ISD::CTTZ) &&
lib/Target/X86/X86TargetTransformInfo.cpp 1913 { ISD::CTTZ, MVT::v8i64, 10 },
1914 { ISD::CTTZ, MVT::v16i32, 14 },
1915 { ISD::CTTZ, MVT::v32i16, 12 },
1916 { ISD::CTTZ, MVT::v64i8, 9 },
1933 { ISD::CTTZ, MVT::v8i64, 20 },
1934 { ISD::CTTZ, MVT::v16i32, 28 },
1974 { ISD::CTTZ, MVT::v4i64, 10 },
1975 { ISD::CTTZ, MVT::v8i32, 14 },
1976 { ISD::CTTZ, MVT::v16i16, 12 },
1977 { ISD::CTTZ, MVT::v32i8, 9 },
2011 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert
2012 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert
2013 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
2014 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
2066 { ISD::CTTZ, MVT::v2i64, 10 },
2067 { ISD::CTTZ, MVT::v4i32, 14 },
2068 { ISD::CTTZ, MVT::v8i16, 12 },
2069 { ISD::CTTZ, MVT::v16i8, 9 }
2087 { ISD::CTTZ, MVT::v2i64, 14 },
2088 { ISD::CTTZ, MVT::v4i32, 18 },
2089 { ISD::CTTZ, MVT::v8i16, 16 },
2090 { ISD::CTTZ, MVT::v16i8, 13 },
2165 ISD = ISD::CTTZ;