reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1026 State.MIs.clear(); 1027 State.MIs.push_back(&I);gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc
445 State.MIs.clear(); 446 State.MIs.push_back(&I);gen/lib/Target/ARM/ARMGenGlobalISel.inc
814 State.MIs.clear(); 815 State.MIs.push_back(&I);gen/lib/Target/Mips/MipsGenGlobalISel.inc
639 State.MIs.clear(); 640 State.MIs.push_back(&I);gen/lib/Target/RISCV/RISCVGenGlobalISel.inc
285 State.MIs.clear(); 286 State.MIs.push_back(&I);gen/lib/Target/X86/X86GenGlobalISel.inc
778 State.MIs.clear(); 779 State.MIs.push_back(&I);include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
93 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 110 if ((size_t)NewInsnID < State.MIs.size()) 111 State.MIs[NewInsnID] = NewMI; 113 assert((size_t)NewInsnID == State.MIs.size() && 115 State.MIs.push_back(NewMI); 142 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 143 unsigned Opcode = State.MIs[InsnID]->getOpcode(); 162 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 163 const int64_t Opcode = State.MIs[InsnID]->getOpcode(); 190 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 191 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 233 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 234 if (State.MIs[InsnID]->getNumOperands() != Expected) { 247 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 248 assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT && 252 if (State.MIs[InsnID]->getOperand(1).isCImm()) 253 Value = State.MIs[InsnID]->getOperand(1).getCImm()->getSExtValue(); 254 else if (State.MIs[InsnID]->getOperand(1).isImm()) 255 Value = State.MIs[InsnID]->getOperand(1).getImm(); 271 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 272 assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT && 276 if (State.MIs[InsnID]->getOperand(1).isCImm()) 277 Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue(); 293 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 294 assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && 296 assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand"); 298 APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF(); 312 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 315 if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID])) 326 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 327 if (!State.MIs[InsnID]->hasOneMemOperand()) 331 for (const auto &MMO : State.MIs[InsnID]->memoperands()) 344 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 345 if (!State.MIs[InsnID]->hasOneMemOperand()) 349 for (const auto &MMO : State.MIs[InsnID]->memoperands()) 362 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 363 if (!State.MIs[InsnID]->hasOneMemOperand()) 367 for (const auto &MMO : State.MIs[InsnID]->memoperands()) 379 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) { 390 = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx); 417 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 419 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) { 426 = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx); 446 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 448 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) { 454 MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx); 482 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 484 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 493 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) { 499 MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx); 525 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 526 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 543 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 544 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 549 MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent(); 573 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 574 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 595 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 599 State.MIs[InsnID]->getOperand(OpIdx)); 616 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 617 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 641 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 642 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 658 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 659 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 673 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 674 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 686 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 687 if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) { 699 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 700 if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) { 711 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 712 if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) { 712 if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) { 727 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 728 assert(State.MIs[OtherInsnID] != nullptr && "Used insn before defined"); 729 if (!State.MIs[InsnID]->getOperand(OpIdx).isIdenticalTo( 730 State.MIs[OtherInsnID]->getOperand(OtherOpIdx))) { 750 OutMIs[NewInsnID] = MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(), 751 State.MIs[OldInsnID]); 766 OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0], 766 OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0], 767 State.MIs[0]->getDebugLoc(), TII.get(Opcode)); 779 OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx)); 793 MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx); 811 OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(), 908 assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT"); 909 if (State.MIs[OldInsnID]->getOperand(1).isCImm()) { 911 State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue()); 912 } else if (State.MIs[OldInsnID]->getOperand(1).isImm()) 913 OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1)); 927 assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT"); 928 if (State.MIs[OldInsnID]->getOperand(1).isFPImm()) 930 State.MIs[OldInsnID]->getOperand(1).getFPImm()); 949 *State.MIs[OldInsnID]); 990 for (const auto &MMO : State.MIs[MergeInsnID]->memoperands()) 999 assert(State.MIs[InsnID] && 1001 State.MIs[InsnID]->eraseFromParent();