|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
1143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
1157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx,
1171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
1185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx,
1199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
1213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs,
1227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs,
1270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p,
1295 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p,
1308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
1338 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1373 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
1422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1457 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx,
1606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
1620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx,
1634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
1648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs,
1662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs,
1683 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
2033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
2060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
2087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
2114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
2137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
2160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
2181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
2201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
2223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
2246 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
2267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
2287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
2309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64,
2331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64,
2349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
2367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
2385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
2403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
2443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2507 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2852 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2915 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
3005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
3025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
3047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32,
3069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32,
3089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
3108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
3126 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
3146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
3165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
3183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
3223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
3246 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
3269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
3292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
3313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
3334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
3379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
3406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
3433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
3460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
3483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3615 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16,
3769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16,
3789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
4013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
4034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
4085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
4100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrx,
4114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
4128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
4142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrs,
4190 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
4194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
4225 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
4229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
4258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
4287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
4318 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
4322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
4353 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
4357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
4386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
4415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
4436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
4451 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrx,
4465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
4479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
4493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrs,
4543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv2i32,
4583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64,
4606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64,
4629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64,
4651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64,
4669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64,
4687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64,
4725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i16,
4765 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32,
4788 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32,
4811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32,
4833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32,
4853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i32,
4872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32,
4890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32,
4928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i8,
4968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16,
4991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16,
5014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16,
5036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16,
5056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i16,
5075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16,
5093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16,
5131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv16i8,
5180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
5200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
5214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDWrrr,
5242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
5262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
5286 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
5290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
5314 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
5318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
5340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
5362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
5376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDXrrr,
5575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs,
5595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs,
5620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8,
5645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16,
5664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWri,
5678 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs,
5692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs,
5712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr,
5732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr,
5769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs,
5789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs,
5812 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB,
5817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
5842 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH,
5847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
5872 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW,
5877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
5902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB,
5907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
5932 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH,
5937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
5962 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW,
5967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
5988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXri,
6002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs,
6016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs,
6036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr,
6056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr,
6222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs,
6242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs,
6261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWri,
6275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs,
6289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs,
6309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr,
6329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr,
6366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs,
6386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs,
6405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXri,
6419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs,
6433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs,
6453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr,
6473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr,
6639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs,
6659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs,
6679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs,
6699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs,
6719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs,
6739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs,
6758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWri,
6772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs,
6786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs,
6806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr,
6826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr,
6846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr,
6860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr,
6897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs,
6917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs,
6937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs,
6957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs,
6977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs,
6997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs,
7016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXri,
7030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs,
7044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs,
7064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr,
7084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr,
7104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr,
7118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr,
7278 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7321 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7324 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7332 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7335 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
7361 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7364 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7372 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7375 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
7422 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7425 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i32_shift,
7462 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7465 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i32_shift,
7502 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7505 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i32_shift,
7542 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7545 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i32_shift,
7582 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7585 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i32_shift,
7622 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7625 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i32_shift,
7662 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7665 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i32_shift,
7697 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7708 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v4i32,
7732 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7735 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v4i32,
7767 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7770 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v4i32,
7802 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7805 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v4i32,
7835 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7838 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i32,
7867 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7870 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv4f32,
7899 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i32,
7931 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7934 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i32,
7960 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7963 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i32,
7990 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7993 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv4i32,
8016 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8037 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8059 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8062 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8070 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8073 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8099 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8102 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8110 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8113 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8160 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8163 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i16_shift,
8200 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8203 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i16_shift,
8240 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8243 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i16_shift,
8280 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8283 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i16_shift,
8320 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8323 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i16_shift,
8360 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8363 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i16_shift,
8400 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8403 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8411 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i16_shift,
8435 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8438 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v8i16,
8470 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8473 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v8i16,
8505 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8508 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v8i16,
8540 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8543 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8551 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v8i16,
8573 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8576 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i16,
8604 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8607 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8615 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv8i16,
8636 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8639 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i16,
8668 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8671 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i16,
8698 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8701 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv8i16,
8724 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8746 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8749 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8757 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8760 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8786 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8789 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8797 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8800 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8847 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8850 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv16i8_shift,
8887 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8890 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv16i8_shift,
8927 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8930 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv16i8_shift,
8967 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8970 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
8978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv16i8_shift,
9007 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9010 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv16i8_shift,
9047 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9050 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv16i8_shift,
9087 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9090 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv16i8_shift,
9122 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9125 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v16i8,
9157 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9160 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v16i8,
9192 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9195 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v16i8,
9227 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9230 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v16i8,
9260 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9263 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv16i8,
9292 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9295 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv16i8,
9324 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9327 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv16i8,
9354 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9357 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv16i8,
9380 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9402 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9405 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9413 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9416 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
9424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
9552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8,
9571 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16,
9590 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32,
9609 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16,
9628 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32,
9706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9885 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10050 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10277 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32,
10281 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32,
10285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10303 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16,
10307 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16,
10311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10329 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16,
10333 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16,
10337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10371 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32,
10375 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32,
10379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10397 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8,
10401 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8,
10405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10446 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32,
10465 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32,
10483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
10965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
11133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11340 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16,
11359 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16,
11377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11791 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32,
11795 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32,
11799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
11869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11969 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32,
11973 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32,
11977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
12047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12215 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12243 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8,
12261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12524 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16,
12528 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16,
12532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
12602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12702 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16,
12706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16,
12710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
12780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12850 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13064 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8,
13068 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8,
13072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8,
13154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHroX,
13271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui,
13284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHi,
13305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX,
13323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroX,
13342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX,
13361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX,
13380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX,
13398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui,
13415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui,
13433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX,
13452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX,
13471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX,
13489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi,
13506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi,
13524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
13542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
13560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui,
13578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
13596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui,
13614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi,
13632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui,
13650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
13668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
13686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
13704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
13722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
13783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX,
13801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
13819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
13837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
13857 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX,
13864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
13884 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX,
13891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
13911 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX,
13918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
13938 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX,
13945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
13963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui,
13980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
13998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX,
14016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi,
14033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui,
14069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi,
14086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
14103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
14120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14156 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui,
14162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14182 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui,
14188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14208 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui,
14214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14234 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui,
14240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14260 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi,
14266 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14286 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi,
14292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14312 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi,
14318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14338 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi,
14344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
14392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
14406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
14432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
14470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
14485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
14499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
14513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
14573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
14588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
14630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
14661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
14676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
14691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
14705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
14719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
14779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
14794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
14836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
14867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX,
14882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
14896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
14927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
14942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
14957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
14985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
14999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
15030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX,
15045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
15059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
15094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWroX,
15112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWroX,
15130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWui,
15147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWui,
15164 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHWi,
15181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBWi,
15200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXroX,
15218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXroX,
15236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWroX,
15254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXui,
15271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXui,
15288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWui,
15305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHXi,
15322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBXi,
15339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSWi,
15364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX,
15382 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX,
15400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX,
15418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui,
15435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
15452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
15469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
15486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
15503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
15520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
15537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
15557 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX,
15564 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15583 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX,
15590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15609 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX,
15616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15635 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX,
15642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15661 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui,
15667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15686 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui,
15692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15711 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui,
15717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15736 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui,
15742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15761 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi,
15767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15786 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi,
15792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15811 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi,
15817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15836 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi,
15842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15861 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi,
15867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15886 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi,
15892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15940 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16,
15968 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16,
15990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHroX,
16006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui,
16021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHi,
16055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32,
16082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32,
16110 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
16117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32,
16145 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
16152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32,
16167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroX,
16183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroX,
16199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui,
16214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui,
16229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi,
16244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi,
16278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64,
16305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64,
16320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroX,
16336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
16352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
16368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
16384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui,
16399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
16414 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
16429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
16444 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi,
16459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
16474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
16489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
16522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
16536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
16549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
16562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
16585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
16602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
16619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
16635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
16651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
16667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
16700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
16717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
16734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
16750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
16766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
16782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
16798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
16831 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
16848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
16865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
16881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
16897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
16913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
16946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
16963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
16980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
16996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
17012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
17028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
17061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX,
17078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
17094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
17127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
17144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
17161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
17177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
17193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
17209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
17242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX,
17259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
17275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
17319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASW,
17341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAW,
17363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLW,
17385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW,
17407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW,
17429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASH,
17451 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAH,
17473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLH,
17495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH,
17517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH,
17539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASB,
17561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAB,
17583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLB,
17605 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB,
17627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB,
17656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASX,
17677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAX,
17698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLX,
17719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX,
17740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX,
17773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPW,
17793 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAW,
17813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLW,
17833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW,
17853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW,
17873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPH,
17893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAH,
17913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLH,
17933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH,
17953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH,
17973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPB,
17993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAB,
18013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLB,
18033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB,
18053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB,
18079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPX,
18098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAX,
18117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLX,
18136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX,
18155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX,
18187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW,
18207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW,
18227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW,
18247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW,
18267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW,
18287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH,
18307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH,
18327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH,
18347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH,
18367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH,
18387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB,
18407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB,
18427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB,
18447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB,
18467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB,
18493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX,
18512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX,
18531 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX,
18550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX,
18569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX,
18602 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW,
18628 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW,
18654 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW,
18680 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW,
18706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW,
18732 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH,
18758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH,
18784 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH,
18810 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18815 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH,
18836 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH,
18862 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB,
18888 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB,
18914 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB,
18940 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB,
18966 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB,
18998 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr,
19003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX,
19023 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr,
19028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX,
19048 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr,
19053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX,
19073 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr,
19078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX,
19098 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr,
19103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX,
19136 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRW,
19162 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAW,
19188 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLW,
19214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW,
19240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW,
19266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRH,
19292 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAH,
19318 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLH,
19344 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH,
19370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH,
19396 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRB,
19422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAB,
19448 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLB,
19474 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB,
19500 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB,
19532 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr,
19537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRX,
19557 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr,
19562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAX,
19582 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr,
19587 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLX,
19607 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr,
19612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX,
19632 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr,
19637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX,
19669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETW,
19689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAW,
19709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLW,
19729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW,
19749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW,
19769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETH,
19789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAH,
19809 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLH,
19829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH,
19849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH,
19869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETB,
19889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAB,
19909 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLB,
19929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB,
19949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB,
19975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETX,
19994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAX,
20013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLX,
20032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX,
20051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX,
20083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORW,
20103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAW,
20123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLW,
20143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW,
20163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW,
20183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORH,
20203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAH,
20223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLH,
20243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH,
20263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH,
20283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORB,
20303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAB,
20323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLB,
20343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB,
20363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB,
20389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORX,
20408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAX,
20427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLX,
20446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX,
20465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX,
20497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXW,
20517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAW,
20537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLW,
20557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW,
20577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW,
20597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXH,
20617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAH,
20637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLH,
20657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH,
20677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH,
20697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXB,
20717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAB,
20737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLB,
20757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB,
20777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB,
20803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXX,
20822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAX,
20841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLX,
20860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX,
20879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX,
20911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINW,
20931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAW,
20951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLW,
20971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW,
20991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW,
21011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINH,
21031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAH,
21051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLH,
21071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH,
21091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH,
21111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINB,
21131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAB,
21151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLB,
21171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB,
21191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB,
21217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINX,
21236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAX,
21255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLX,
21274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX,
21293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX,
21325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXW,
21345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAW,
21365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLW,
21385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW,
21405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW,
21425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXH,
21445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAH,
21465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLH,
21485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH,
21505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH,
21525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXB,
21545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAB,
21565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLB,
21585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB,
21605 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB,
21631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXX,
21650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAX,
21669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLX,
21688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX,
21707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX,
21739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINW,
21759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAW,
21779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLW,
21799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW,
21819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW,
21839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINH,
21859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAH,
21879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLH,
21899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH,
21919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH,
21939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINB,
21959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAB,
21979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLB,
21999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB,
22019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB,
22045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINX,
22064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAX,
22083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLX,
22102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX,
22121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX,
22147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB,
22163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS,
22190 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESErr,
22195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrrTied,
22220 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESDrr,
22225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrrTied,
22241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FJCVTZS,
22257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWHr,
22273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXHr,
22289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr,
22305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr,
22321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr,
22337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr,
22353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWHr,
22369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXHr,
22385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr,
22401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr,
22417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr,
22433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr,
22449 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWHr,
22465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXHr,
22481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr,
22497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr,
22513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr,
22529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr,
22545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWHr,
22561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXHr,
22577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr,
22593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr,
22609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr,
22625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr,
22641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWHr,
22657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXHr,
22673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWSr,
22689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXSr,
22705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWDr,
22721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXDr,
22737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWHr,
22753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXHr,
22769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWSr,
22785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXSr,
22801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWDr,
22817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXDr,
22833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWHr,
22849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXHr,
22865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr,
22881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr,
22897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr,
22913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr,
22929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWHr,
22945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXHr,
22961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr,
22977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr,
22993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr,
23009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr,
23025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNHr,
23041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNSr,
23057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr,
23073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i8,
23089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv16i8,
23105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i16,
23121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i16,
23137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv2i32,
23153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i32,
23169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f16,
23185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv8f16,
23201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f32,
23217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f32,
23233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f64,
23249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f16,
23265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv8f16,
23281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f32,
23297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f32,
23313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f64,
23329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f16,
23345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv8f16,
23361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f32,
23377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f32,
23393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f64,
23409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f16,
23425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv8f16,
23441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f32,
23457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f32,
23473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f64,
23489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f16,
23505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv8f16,
23521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f32,
23537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f32,
23553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f64,
23569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f16,
23585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv8f16,
23601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f32,
23617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f32,
23633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f64,
23649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f16,
23665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv8f16,
23681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f32,
23697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f32,
23713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f64,
23729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f16,
23745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv8f16,
23761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f32,
23777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f32,
23793 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f64,
23809 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv2f32,
23825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f16,
23841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv8f16,
23857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f32,
23873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f32,
23889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f64,
23905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f16,
23921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv8f16,
23937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f32,
23953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f32,
23969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f64,
23985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f16,
24001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv8f16,
24017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f32,
24033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f32,
24049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f64,
24065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv8i8,
24081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv16i8,
24097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i8_v4i16,
24113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv16i8_v8i16,
24129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i16_v2i32,
24145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i16_v4i32,
24161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv2i32_v1i64,
24177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i32_v2i64,
24193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i8,
24209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv16i8,
24225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i16,
24241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i16,
24257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i32,
24273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i32,
24289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i64,
24305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i8,
24321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv16i8,
24337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i16,
24353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i16,
24369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i32,
24385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i32,
24401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i64,
24417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i8,
24433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i16,
24449 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv2i32,
24465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i8,
24481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i16,
24497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv2i32,
24513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i8_v4i16,
24529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv16i8_v8i16,
24545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i16_v2i32,
24561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i16_v4i32,
24577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv2i32_v1i64,
24593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i32_v2i64,
24609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i8,
24625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i16,
24641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv2i32,
24657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv2i32,
24673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv4i32,
24689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv2i32,
24705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv4i32,
24721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv1i64,
24737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64,
24753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i32,
24769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64,
24785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i32,
24801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv1i32,
24817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv1i32,
24833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv1i32,
24849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i16v,
24865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv8i16v,
24881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i32v,
24897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i16v,
24913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv8i16v,
24929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i32v,
24945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i16v,
24961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv8i16v,
24977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i32v,
24993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i16v,
25009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv8i16v,
25025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i32v,
25041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrr,
25057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrr,
25073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Hrr,
25089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64,
25104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr,
25119 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr,
25134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTLv4i16,
25149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i16,
25165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64,
25180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv1i64,
25195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv1i64,
25210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv1i64,
25225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv1i64,
25240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv1i64,
25255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv1i64,
25270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv1i64,
25285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv1i64,
25300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1f16,
25315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i32,
25330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64,
25345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64,
25360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1f16,
25375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i32,
25390 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i64,
25405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1f16,
25420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i32,
25435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64,
25450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64,
25465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p,
25480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p,
25495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i32p,
25510 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i64p,
25525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i32p,
25540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i64p,
25555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i32p,
25570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i64p,
25585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i32p,
25600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i64p,
25618 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv8i8v,
25622 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25625 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
25633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32,
25652 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv16i8v,
25656 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25659 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
25667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32,
25709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv1i64_indexed,
25749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv1i64_indexed,
25789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHi32_indexed,
25829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHi32_indexed,
25861 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
25866 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh,
25893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16,
25921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16,
25949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32,
25977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32,
26005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16,
26033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16,
26061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32,
26089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32,
26117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_v4i32,
26145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_v2i64,
26173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_v4i32,
26201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_v2i64,
26229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv1i32,
26257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv1i32,
26284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALi32,
26311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLi32,
26342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed,
26373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed,
26404 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed,
26435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed,
26466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed,
26497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed,
26528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32_indexed,
26559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32_indexed,
26589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv1i64_indexed,
26614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNs,
26638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNs,
26662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNs,
26686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNs,
26710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNs,
26734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNs,
26758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i8_shift,
26782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i16_shift,
26806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv2i32_shift,
26830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i8_shift,
26854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i16_shift,
26878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv2i32_shift,
26902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i8_shift,
26926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i16_shift,
26950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv2i32_shift,
26974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i8_shift,
26998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i16_shift,
27022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv2i32_shift,
27046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i8_shift,
27070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i16_shift,
27094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv2i32_shift,
27118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i8_shift,
27142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i16_shift,
27166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv2i32_shift,
27190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i8_shift,
27214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i16_shift,
27238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv2i32_shift,
27261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSs,
27284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUs,
27307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd,
27330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd,
27353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd,
27376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd,
27399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFs,
27422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd,
27445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd,
27468 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd,
27491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd,
27514 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFs,
27538 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh,
27567 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh,
27596 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh,
27625 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh,
27655 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh,
27660 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
27691 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh,
27696 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
27727 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh,
27732 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
27763 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh,
27768 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
27797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i16_shift,
27820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv8i16_shift,
27843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i32_shift,
27866 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i32_shift,
27889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i64_shift,
27912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i16_shift,
27935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv8i16_shift,
27958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i32_shift,
27981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i32_shift,
28004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i64_shift,
28027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i16_shift,
28050 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv8i16_shift,
28073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i32_shift,
28096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i32_shift,
28119 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i64_shift,
28142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i16_shift,
28165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv8i16_shift,
28188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i32_shift,
28211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i32_shift,
28234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i64_shift,
28253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Brr,
28272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Hrr,
28291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Wrr,
28310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Xrr,
28329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CBrr,
28348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CHrr,
28367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CWrr,
28386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CXrr,
28405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i8,
28424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv16i8,
28443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i16,
28462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i16,
28481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i32,
28500 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i32,
28519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i64,
28538 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i8,
28557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv16i8,
28576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i16,
28595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i16,
28614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i32,
28633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i32,
28652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i64,
28671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i8,
28690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv16i8,
28709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i16,
28728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i16,
28747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i32,
28766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i32,
28785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64,
28804 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16,
28823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16,
28842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32,
28861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32,
28880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64,
28899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f16,
28918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv8f16,
28937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f32,
28956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f32,
28975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f64,
28994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f16,
29013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv8f16,
29032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f32,
29051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f32,
29070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f64,
29089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f16,
29108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv8f16,
29127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f32,
29146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f32,
29165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f64,
29184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f16,
29203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv8f16,
29222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f32,
29241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f32,
29260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f64,
29279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f16,
29298 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv8f16,
29317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f32,
29336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f32,
29355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f64,
29374 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f16,
29393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv8f16,
29412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f32,
29431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f32,
29450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f64,
29469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f16,
29488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv8f16,
29507 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f32,
29526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f32,
29545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f64,
29564 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f16,
29583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8f16,
29602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f32,
29621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f32,
29640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f64,
29659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f16,
29678 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv8f16,
29697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f32,
29716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f32,
29735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f64,
29754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f16,
29773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv8f16,
29792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f32,
29811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f32,
29830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f64,
29849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv8i8,
29868 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv16i8,
29887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i8,
29906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv16i8,
29925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i16,
29944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i16,
29963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv2i32,
29982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i32,
30001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv8i8,
30020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv16i8,
30039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv4i16,
30058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv8i16,
30077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv2i32,
30096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv4i32,
30115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i8,
30134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv16i8,
30153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i16,
30172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i16,
30191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv2i32,
30210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i32,
30229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i8,
30248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv16i8,
30267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i16,
30286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i16,
30305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv2i32,
30324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i32,
30343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i8,
30362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv16i8,
30381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i16,
30400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i16,
30419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv2i32,
30438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i32,
30457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i8,
30476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv16i8,
30495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i16,
30514 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i16,
30533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i32,
30552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i32,
30571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i64,
30590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i16,
30609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv8i16,
30628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv2i32,
30647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i32,
30666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i16,
30685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv8i16,
30704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv2i32,
30723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i32,
30742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i8,
30761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv16i8,
30780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i16,
30799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i16,
30818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i32,
30837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i32,
30856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i64,
30875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i8,
30894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv16i8,
30913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i16,
30932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i16,
30951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i32,
30970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i32,
30989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i64,
31008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i8,
31027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv16i8,
31046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i16,
31065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i16,
31084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i32,
31103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i32,
31122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i64,
31141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv8i8,
31160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv16i8,
31179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv4i16,
31198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv8i16,
31217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv2i32,
31236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv4i32,
31255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i8,
31274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv16i8,
31293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i16,
31312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i16,
31331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i32,
31350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i32,
31369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i64,
31388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i8,
31407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv16i8,
31426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i16,
31445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i16,
31464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i32,
31483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i32,
31502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i64,
31521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i8,
31540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv16i8,
31559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i16,
31578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i16,
31597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv2i32,
31616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i32,
31635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv8i8,
31654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv16i8,
31673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv4i16,
31692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv8i16,
31711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv2i32,
31730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv4i32,
31749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i8,
31768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv16i8,
31787 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i16,
31806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i16,
31825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv2i32,
31844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i32,
31863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i8,
31882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv16i8,
31901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i16,
31920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i16,
31939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv2i32,
31958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i32,
31977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i8,
31996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv16i8,
32015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i16,
32034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i16,
32053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv2i32,
32072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i32,
32091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i8,
32110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv16i8,
32129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i16,
32148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i16,
32167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i32,
32186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i32,
32205 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i64,
32224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i8,
32243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv16i8,
32262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i16,
32281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i16,
32300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i32,
32319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i32,
32338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i64,
32357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i8,
32376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv16i8,
32395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i16,
32414 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i16,
32433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i32,
32452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i32,
32471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i64,
32490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i8,
32509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv16i8,
32528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i16,
32547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i16,
32566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i32,
32585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i32,
32604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i64,
32623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv8i8,
32642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv16i8,
32661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv4i16,
32680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv8i16,
32699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv2i32,
32718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv4i32,
32737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i8,
32756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv16i8,
32775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i16,
32794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i16,
32813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i32,
32832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i32,
32851 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i64,
32870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i8,
32889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv16i8,
32908 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i16,
32927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i16,
32946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i32,
32965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i32,
32984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i64,
33003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64,
33022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32,
33041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16,
33060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64,
33079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE32,
33098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64,
33117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT32,
33136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64,
33155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX32,
33174 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX16,
33193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64,
33212 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS32,
33231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS16,
33250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64,
33269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS32,
33288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS16,
33307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64,
33326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32,
33345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32,
33364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64,
33383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64,
33402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64,
33421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64,
33440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64,
33459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64,
33478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64,
33497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64,
33516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64,
33535 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64,
33554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64,
33573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLi32,
33592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64,
33611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i32,
33630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64,
33649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i32,
33668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v8i8,
33687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v4i16,
33706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v2i32,
33725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v8i8,
33744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v4i16,
33763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v2i32,
33782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v8i8,
33801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v4i16,
33820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v2i32,
33839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v8i8,
33858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v4i16,
33877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v2i32,
33896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv8i8,
33915 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv8i8_v8i16,
33934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv4i16_v4i32,
33953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv2i32_v2i64,
33972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv4i16_v4i32,
33991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv2i32_v2i64,
34010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv8i8_v8i16,
34029 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv4i16_v4i32,
34048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv2i32_v2i64,
34067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESErr,
34086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESDrr,
34105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU1rr,
34124 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU0rr,
34143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64,
34162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i32,
34181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64,
34200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64,
34219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64,
34237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVWr,
34255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVXr,
34273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVWr,
34291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVXr,
34309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64,
34328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64,
34347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64,
34366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64,
34385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64,
34404 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64,
34423 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i32,
34442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64,
34461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i32,
34480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64,
34499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i32,
34518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64,
34537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i32,
34556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64,
34575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i32,
34594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64,
34613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i32,
34632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64,
34651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i32,
34670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64,
34688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv1i64,
34706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv8i8One,
34724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv16i8One,
34744 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGE16,
34749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
34752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
34775 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGT16,
34780 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
34783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
34804 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64,
34822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64,
34840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64,
34858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64,
34878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::GMI,
34899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBP,
34929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i8_shift,
34956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv16i8_shift,
34983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i16_shift,
35010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i16_shift,
35037 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i32_shift,
35064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i32_shift,
35091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i64_shift,
35118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i8_shift,
35145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv16i8_shift,
35172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i16_shift,
35199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i16_shift,
35226 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i32_shift,
35253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i32_shift,
35280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i64_shift,
35306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLId,
35332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRId,
35354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv8i8,
35376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv16i8,
35398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv8i8,
35420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv16i8,
35442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv4f16,
35464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv8f16,
35486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv4f16,
35508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv8f16,
35530 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v4f16,
35552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v8f16,
35574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v4f16,
35596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v8f16,
35618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Crrr,
35640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Prrr,
35662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Mrrr,
35684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU0rrr,
35706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256Hrrr,
35728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256H2rrr,
35750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU1rrr,
35771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv8i8One,
35792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv16i8One,
35829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi8lane,
35862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane,
35895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane,
35928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
35947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCOMMIT,
35957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLREX,
35977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HINT,
35995 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB,
36013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DSB,
36031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ISB,
36045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCANCEL,
36059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TSTART,
36073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TTEST,
36094 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB,
36099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
36120 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH,
36125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
36146 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW,
36151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
36171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDXRX,
36190 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB,
36195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
36216 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH,
36221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
36242 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW,
36247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
36267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDAXRX,
36283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRGstack,
36317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB,
36348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH,
36379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB,
36410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH,
36438 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB,
36471 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH,
36504 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW,
36537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB,
36570 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH,
36603 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW,
36633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW,
36658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW,
36681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SPACE,
36702 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS,
36725 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES,
36749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB,
36776 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH,
36803 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW,
36829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRX,
36851 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB,
36878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH,
36905 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW,
36931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRX,
36952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRG,
36977 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
36980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
36999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift,
37015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift,
37031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift,
37055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
37116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi32imm,
37134 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
37138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
37154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi64imm,
37178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVH0,
37193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVS0,
37208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVD0,
37242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi32to64,
37256 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37259 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
37267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri,
37286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv2i32_shift,
37302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv4i16_shift,
37318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv8i8_shift,
37351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv2i32_v2i64,
37372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv2i32_v2i64,
37384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift,
37412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv4i16_v4i32,
37433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv4i16_v4i32,
37445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift,
37473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16,
37494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv8i8_v8i16,
37506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift,
37537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr,
37553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr,
37569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr,
37595 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
37602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr,
37619 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
37626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr,
37666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMWri,
37683 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr,
37699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr,
37715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr,
37741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMXri,
37759 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
37766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr,
37783 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
37790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr,
37830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMWri,
37847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr,
37863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr,
37879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr,
37911 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37914 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
37922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri,
37941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri,
37960 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
37967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr,
37985 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
37992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr,
38047 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv4i32_v2i64,
38052 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38057 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38062 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv2i32_v2i64,
38067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32,
38089 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv8i16_v4i32,
38094 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38099 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38104 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv4i16_v4i32,
38109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16,
38131 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv16i8_v8i16,
38136 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38141 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38146 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv8i8_v8i16,
38151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8,
38195 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv4i32_v2i64,
38200 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38205 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38210 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv2i32_v2i64,
38215 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32,
38237 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv8i16_v4i32,
38242 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38252 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv4i16_v4i32,
38257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16,
38279 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv16i8_v8i16,
38284 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38289 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38294 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv8i8_v8i16,
38299 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8,
38358 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
38363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p,
38388 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
38393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p,
38435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p,
38459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p,
38762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed,
38788 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed,
38832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed,
38858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed,
38902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed,
38928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed,
39058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr,
39082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr,
39102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr,
39122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr,
39142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBHrrr,
39192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39257 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
39264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39329 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
39336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39401 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
39408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39504 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
39511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed,
39568 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
39575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed,
39603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed,
39632 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
39639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed,
39663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr,
39686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr,
39705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr,
39725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr,
39745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBSrrr,
39795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed,
39827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed,
39859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed,
39891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed,
39922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed,
39954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed,
39982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed,
40010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed,
40034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr,
40057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr,
40076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr,
40096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr,
40116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBDrrr,
40155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32,
40175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32,
40191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f32,
40219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64,
40239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64,
40255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f64,
40284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16,
40299 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f16,
40327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32,
40347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32,
40363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f32,
40392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16,
40407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8f16,
40580 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr,
40600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr,
40637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr,
40657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr,
40694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr,
40714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr,
40958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr,
40974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr,
40990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr,
41006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr,
41057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr,
41073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr,
41089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr,
41105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr,
41232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr,
41248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr,
41264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr,
41280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr,
41331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr,
41347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr,
41363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr,
41379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr,
41686 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX,
41693 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41696 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32,
41726 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui,
41732 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41735 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32,
41765 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi,
41771 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41774 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32,
41828 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSroX,
41835 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41838 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64,
41868 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX,
41875 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64,
41908 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSui,
41914 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41917 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64,
41947 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURSi,
41953 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41956 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64,
41986 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui,
41992 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
42003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64,
42025 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi,
42031 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
42034 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
42042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64,
42162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16,
42194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32,
42226 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64,
42259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32,
42292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64,
42325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16,
42358 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32,
42391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16,
43127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi16,
43151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8,
43173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16,
43195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi32,
43216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi32,
43241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi64,
43260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi64,
43285 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITWr,
43289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZWr,
43305 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITXr,
43309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZXr,
43361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr,
43396 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr,
43446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr,
43481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BCNT_U32_B32_e64,
631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BCNT_U32_B32_e64,
824 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
860 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
896 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
932 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
968 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1040 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1076 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1112 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1148 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1184 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1220 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1256 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1292 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1328 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1333 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1364 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B32,
1499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B64,
1545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2156 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2314 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2396 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
2546 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
2565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
2586 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
2606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
2627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
2649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
2670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
2698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
2720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
2739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
2760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
2780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
2801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
2823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
2844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
2867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
2888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
2908 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
2929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
2951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
2971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
2991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
3013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
3036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
3057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
3077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
3098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
3120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
3140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
3160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
3182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
3210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
3232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
3251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
3272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
3292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
3313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
3335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
3356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
3379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
3400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
3420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
3441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
3463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
3483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
3503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
3525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
3548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
3569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
3589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
3610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
3632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
3652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
3672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
3694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
3718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
3734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
3749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
3764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
3789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFSET,
3813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_USHORT_OFFSET,
3838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFEN,
3863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_USHORT_OFFEN,
3891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U8,
3912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U8_gfx9,
3933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U16,
3953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U16_gfx9,
3974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_UBYTE,
3996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_USHORT,
4019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_UBYTE,
4041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_USHORT,
4064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
4085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
4105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
4125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
4146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
4166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
4187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
4208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
4229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFSET,
4254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_USHORT_OFFSET,
4278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4374 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFEN,
4497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_USHORT_OFFEN,
4522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
4724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
4745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
4767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U8,
4789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U16,
4810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U8_gfx9,
4831 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U16_gfx9,
4852 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
4873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
4893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
4913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
4934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
4957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_UBYTE,
4980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_USHORT,
5002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
5024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
5047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
5070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_UBYTE,
5093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_USHORT,
5115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
5137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
5165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
5189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
5208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
5229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
5249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
5269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
5290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
5310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
5333 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
5355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
5375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
5396 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
5418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
5439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
5458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
5479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
5499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
5521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
5543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
5565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
5587 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
5609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
5631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
5653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
5676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
5697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
5717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
5737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
5758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM_ci,
5778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_SGPR,
5799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
5820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORD_IMM,
5842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
5863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32,
5883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
5903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B32_gfx9,
5923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
5945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORD,
5967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
5989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORD,
6017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
6041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
6060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
6101 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
6121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
6162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
6185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
6207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
6227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET,
6292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN,
6318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
6340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
6362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
6384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
6408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
6424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM_ci,
6439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_SGPR,
6454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
6470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM_ci,
6485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_SGPR,
6500 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
6515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
6539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET,
6563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN,
6589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX3,
6611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX3,
6639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
6663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64,
6682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
6723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
6743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM_ci,
6784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_SGPR,
6807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
6829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B64_gfx9,
6849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX2_IMM,
6891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
6913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX2,
6935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
6957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX2,
6985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B128,
7004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
7025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM_ci,
7045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_SGPR,
7065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
7086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM_ci,
7106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_SGPR,
7129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_B128_gfx9,
7149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
7170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX4_IMM,
7190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET,
7214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN,
7240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_DWORDX4,
7262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_DWORDX4,
7286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX8_IMM,
7302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX8_IMM_ci,
7317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX8_SGPR,
7332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX8_IMM,
7357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX16_IMM,
7373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX16_IMM_ci,
7388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX16_SGPR,
7403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_LOAD_DWORDX16_IMM,
7433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_SBYTE_OFFSET,
7457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_SBYTE_OFFEN,
7483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_I8_gfx9,
7503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_SBYTE,
7525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_SBYTE,
7548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_SBYTE_OFFSET,
7572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_SSHORT_OFFSET,
7596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_SBYTE_OFFEN,
7621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_SSHORT_OFFEN,
7647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_I8_gfx9,
7667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_I16_gfx9,
7687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_I16_gfx9,
7707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_SBYTE,
7729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_SSHORT,
7751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_SBYTE,
7773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_SSHORT,
7802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFSET,
7826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFEN,
7852 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U8_gfx9,
7872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_UBYTE,
7894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_UBYTE,
7917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFSET,
7941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_USHORT_OFFSET,
7965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_UBYTE_OFFEN,
7990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_USHORT_OFFEN,
8016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U8_gfx9,
8036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_READ_U16_gfx9,
8056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_UBYTE,
8078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_LOAD_USHORT,
8100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_UBYTE,
8122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_LOAD_USHORT,
8167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
8188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
8207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
8228 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
8254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
8275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
8294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
8315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
8337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
8360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
8386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
8405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
8424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
8445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
8467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
8490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
8516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
8535 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
8554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
8575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
8601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
8622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
8641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
8662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
8684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
8707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
8733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
8752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
8771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
8792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
8814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
8837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
8863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
8882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
8901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
8922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
8945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_BYTE_OFFSET,
8968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_SHORT_OFFSET,
8992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_BYTE_OFFEN,
9016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_SHORT_OFFEN,
9042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B8_gfx9,
9062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B16,
9082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
9102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
9121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B8,
9140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B16_gfx9,
9159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
9178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
9198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_BYTE,
9219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_SHORT,
9241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_BYTE,
9262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_SHORT,
9285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_BYTE_OFFSET,
9309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_SHORT_OFFSET,
9332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
9355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
9379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_BYTE_OFFEN,
9404 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_SHORT_OFFEN,
9428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
9452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
9478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B8_gfx9,
9498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B16_gfx9,
9518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
9538 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
9557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B8,
9576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B16,
9595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
9614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
9634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_BYTE,
9656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_SHORT,
9677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
9698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
9720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_BYTE,
9742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_SHORT,
9763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
9784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
9810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
9832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
9853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
9874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
9893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
9914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
9935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
9956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
9978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
10001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
10024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
10048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFEN,
10074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
10094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32,
10113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
10132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B32_gfx9,
10151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
10172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORD,
10193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
10214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORD,
10240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
10262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
10283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
10304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
10322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORDX2_OFFSET,
10345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORDX2_OFFEN,
10370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
10391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
10412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
10433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
10455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORDX3_OFFSET,
10478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORDX3_OFFEN,
10503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX3,
10524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX3,
10550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
10572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64,
10593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
10614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B64_gfx9,
10633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
10654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX2,
10675 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
10696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX2,
10722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B128,
10743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRITE_B128_gfx9,
10761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORDX4_OFFSET,
10784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORDX4_OFFEN,
10809 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_STORE_DWORDX4,
10830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_STORE_DWORDX4,
10862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_CMPST_RTN_B32,
10883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_CMPST_RTN_B32_gfx9,
10903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_CMPST_RTN_B32,
10931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_CMPST_RTN_B64,
10952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_CMPST_RTN_B64_gfx9,
10972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_CMPST_RTN_B64,
11005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRXCHG_RTN_B32,
11025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRXCHG_RTN_B32_gfx9,
11044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRXCHG_RTN_B32,
11064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SWAP_RTN,
11084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SWAP_RTN,
11110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRXCHG_RTN_B64,
11130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRXCHG_RTN_B64_gfx9,
11149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_WRXCHG_RTN_B64,
11169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN,
11189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN,
11221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_U32,
11241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_U32_gfx9,
11260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_U32,
11280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_ADD_RTN,
11300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_ADD_RTN,
11326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_U64,
11346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_U64_gfx9,
11365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_U64,
11385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_ADD_X2_RTN,
11405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN,
11437 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_SUB_RTN_U32,
11457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_SUB_RTN_U32_gfx9,
11476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_SUB_RTN_U32,
11496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SUB_RTN,
11516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SUB_RTN,
11542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_SUB_RTN_U64,
11562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_SUB_RTN_U64_gfx9,
11581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_SUB_RTN_U64,
11601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SUB_X2_RTN,
11621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN,
11653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_AND_RTN_B32,
11673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_AND_RTN_B32_gfx9,
11692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_AND_RTN_B32,
11712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_AND_RTN,
11732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_AND_RTN,
11758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_AND_RTN_B64,
11778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_AND_RTN_B64_gfx9,
11797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_AND_RTN_B64,
11817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_AND_X2_RTN,
11837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN,
11869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_OR_RTN_B32,
11889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_OR_RTN_B32_gfx9,
11908 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_OR_RTN_B32,
11928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_OR_RTN,
11948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_OR_RTN,
11974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_OR_RTN_B64,
11994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_OR_RTN_B64_gfx9,
12013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_OR_RTN_B64,
12033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_OR_X2_RTN,
12053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN,
12085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_XOR_RTN_B32,
12105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_XOR_RTN_B32_gfx9,
12124 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_XOR_RTN_B32,
12144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_XOR_RTN,
12164 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_XOR_RTN,
12190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_XOR_RTN_B64,
12210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_XOR_RTN_B64_gfx9,
12229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_XOR_RTN_B64,
12249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_XOR_X2_RTN,
12269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN,
12301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_I32,
12321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_I32_gfx9,
12340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_I32,
12360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SMAX_RTN,
12380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SMAX_RTN,
12406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_I64,
12426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_I64_gfx9,
12445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_I64,
12465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN,
12485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN,
12517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_I32,
12537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_I32_gfx9,
12556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_I32,
12576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SMIN_RTN,
12596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SMIN_RTN,
12622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_I64,
12642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_I64_gfx9,
12661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_I64,
12681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN,
12701 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN,
12733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_U32,
12753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_U32_gfx9,
12772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_U32,
12792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_UMAX_RTN,
12812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_UMAX_RTN,
12838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_U64,
12858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_U64_gfx9,
12877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MAX_RTN_U64,
12897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN,
12917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN,
12949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_U32,
12969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_U32_gfx9,
12988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_U32,
13008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_UMIN_RTN,
13028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_UMIN_RTN,
13054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_U64,
13074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_U64_gfx9,
13093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_MIN_RTN_U64,
13113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN,
13133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN,
13163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_F32,
13179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_F32_gfx9,
13200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_ADD_RTN_F32,
13230 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::ATOMIC_FENCE,
13247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_GETPC_B64,
13259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GET_GROUPSTATICSIZE,
13271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_PS_LIVE,
13288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_FLBIT_I32,
13302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READFIRSTLANE_B32,
13317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FRACT_F32_e64,
13335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RCP_F32_e64,
13353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RSQ_F32_e64,
13371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RCP_F64_e64,
13389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RSQ_F64_e64,
13407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SIN_F32_e64,
13425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_COS_F32_e64,
13443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F64_e64,
13461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F64_e64,
13479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FRACT_F64_e64,
13497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F32_e64,
13515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F32_e64,
13534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_CLAMP_F32_e64,
13553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RCP_LEGACY_F32_e64,
13572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RSQ_CLAMP_F32_e64,
13591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RSQ_LEGACY_F32_e64,
13610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RSQ_CLAMP_F64_e64,
13629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RCP_F16_e64,
13648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RSQ_F16_e64,
13667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SIN_F16_e64,
13686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_COS_F16_e64,
13705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F16_e64,
13724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I16_F16_e64,
13743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FRACT_F16_e64,
13760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FFBH_I32_e64,
13781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_PERMUTE_B32,
13800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::DS_BPERMUTE_B32,
13817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READLANE_B32,
13833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B32,
13849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B64,
13867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LDEXP_F32_e64,
13889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKNORM_I16_F32_e64,
13910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKNORM_U16_F32_e64,
13931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e64,
13954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LDEXP_F16_e64,
13976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LDEXP_F64,
13997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_CLASS_F32_e64,
14015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMPX_CLASS_F32_e64,
14033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_CLASS_F64_e64,
14051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMPX_CLASS_F64_e64,
14070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_CLASS_F16_e64,
14089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMPX_CLASS_F16_e64,
14106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_LO_U32_B32_e64,
14122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_HI_U32_B32_e64,
14138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_U16_U32_e64,
14154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_I16_I32_e64,
14175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_WRITELANE_B32,
14193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U8,
14212 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_HI_U8,
14231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U16,
14250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MSAD_U8,
14269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_PK_U16_U8,
14288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_QSAD_PK_U16_U8,
14307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_U32_U8,
14329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEID_F32,
14355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBESC_F32,
14381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBETC_F32,
14407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEMA_F32,
14433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MED3_F32,
14459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_U8_F32,
14485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MED3_F16,
14508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LERP_U8,
14526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBIT_B32,
14544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBYTE_B32,
14575 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_INTERP_MOV_F32,
14601 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_INTERP_P1_F32,
14627 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_INTERP_P1_F32_16bank,
14656 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_INTERP_P2_F32,
14687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_4X4X1F32,
14715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_4X4X4F16,
14743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_I32_4X4X4I8,
14771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_4X4X2BF16,
14799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_16X16X1F32,
14827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_16X16X4F32,
14855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_16X16X4F16,
14883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_16X16X16F16,
14911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_I32_16X16X4I8,
14939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_I32_16X16X16I8,
14967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_16X16X2BF16,
14995 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_16X16X8BF16,
15023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_32X32X1F32,
15051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_32X32X2F32,
15079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_32X32X4F16,
15107 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_32X32X8F16,
15135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_I32_32X32X4I8,
15163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_I32_32X32X8I8,
15191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_32X32X2BF16,
15219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MFMA_F32_32X32X4BF16,
15239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_BARRIER,
15248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV,
15259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV_VOL,
15270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB,
15281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB_VOL,
15292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_SC,
15302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1,
15313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_VOL,
15323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::WAVE_BARRIER,
15333 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_MASKED_UNREACHABLE,
15347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_WAITCNT,
15360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_SLEEP,
15373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_INCPERFLEVEL,
15386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DECPERFLEVEL,
15400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_INIT_EXEC,
15413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMTIME,
15427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMREALTIME,
15441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_GET_WAVEID_IN_WORKGROUP,
15460 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
15463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_SENDMSG,
15477 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
15480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_SENDMSGHALT,
15493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_INIT_EXEC_FROM_INPUT,
15515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
15530 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
15553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LSHLREV_B16_e64,
15581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LSHLREV_B32_e64,
15632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LSHLREV_B64,
15658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LSHRREV_B16_e64,
15686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LSHRREV_B32_e64,
15737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LSHRREV_B64,
15763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I16_e64,
15791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e64,
15842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I64,
15872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_I16_e64,
15886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_I16_e64,
15900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_I16_e64,
15914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_I16_e64,
15928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_U16_e64,
15942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_U16_e64,
15956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_U16_e64,
15970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_U16_e64,
15984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NE_U16_e64,
15998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_U16_e64,
16018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_I32_e64,
16031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_I32_e64,
16044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_I32_e64,
16057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_I32_e64,
16077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_I64_e64,
16090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_I64_e64,
16103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_I64_e64,
16116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_I64_e64,
16140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_U32_e64,
16153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_U32_e64,
16166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_U32_e64,
16179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_U32_e64,
16192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NE_U32_e64,
16205 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_U32_e64,
16225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_U64_e64,
16238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_U64_e64,
16251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_U64_e64,
16264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_U64_e64,
16277 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NE_U64_e64,
16290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_U64_e64,
16324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_F16_e64,
16343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F16_e64,
16362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_F16_e64,
16381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_F16_e64,
16400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LG_F16_e64,
16419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_F16_e64,
16438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_O_F16_e64,
16457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_U_F16_e64,
16476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NGE_F16_e64,
16495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLG_F16_e64,
16514 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NGT_F16_e64,
16533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLE_F16_e64,
16552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NEQ_F16_e64,
16571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLT_F16_e64,
16596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_F32_e64,
16614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
16632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_F32_e64,
16650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_F32_e64,
16668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LG_F32_e64,
16686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_F32_e64,
16704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_O_F32_e64,
16722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_U_F32_e64,
16740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NGE_F32_e64,
16758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLG_F32_e64,
16776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NGT_F32_e64,
16794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLE_F32_e64,
16812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NEQ_F32_e64,
16830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLT_F32_e64,
16855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LT_F64_e64,
16873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
16891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LE_F64_e64,
16909 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GT_F64_e64,
16927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_LG_F64_e64,
16945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_GE_F64_e64,
16963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_O_F64_e64,
16981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_U_F64_e64,
16999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NGE_F64_e64,
17017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLG_F64_e64,
17035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NGT_F64_e64,
17053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLE_F64_e64,
17071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NEQ_F64_e64,
17089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_NLT_F64_e64,
17151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
17169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
17194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
17211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
17236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
17253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
17284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F16_e64,
17306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F32_e64,
17337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
17355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
17380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
17397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
17422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
17439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
17474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F16,
17495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F16_gfx9,
17523 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F32,
17549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F64,
17582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_F16,
17608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_F32,
17635 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_LOG_F32_e32,
17639 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_MUL_LEGACY_F32_e32,
17644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e32,
17664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F16_e64,
17682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e64,
17707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F16_e64,
17725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F32_e64,
17757 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
17779 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
17797 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_XOR_B32,
17815 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_XOR_B32_e32,
17843 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
17861 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_XOR_B32,
17879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_XOR_B32_e32,
17910 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B32_e32,
17914 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
17919 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_OR_B32_e32,
17924 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
17929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
17947 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B32_e32,
17951 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
17956 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_XOR_B32_e32,
17961 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
17966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
17992 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
18014 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
18032 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_XOR_B32,
18050 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_XOR_B32_e32,
18078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F16_e64,
18096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_F32_e64,
18120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e64,
18138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F64_e64,
18163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
18180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
18200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I16_F16_e64,
18218 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CVT_F32_F16_e32,
18222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F32_e32,
18235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F64_e64,
18251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F32_e64,
18276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
18293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
18313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U16_F16_e64,
18331 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CVT_F32_F16_e32,
18335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F32_e32,
18348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F64_e64,
18364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F32_e64,
18389 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CVT_F32_I32_e32,
18393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e32,
18406 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CNDMASK_B32_e64,
18414 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e32,
18428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_I16_e64,
18444 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CNDMASK_B32_e64,
18461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_I32_e64,
18478 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CNDMASK_B32_e64,
18486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_I32_e32,
18499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_I32_e64,
18523 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CVT_F32_U32_e32,
18527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e32,
18540 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CNDMASK_B32_e64,
18548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e32,
18562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_U16_e64,
18578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CNDMASK_B32_e64,
18595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_U32_e64,
18612 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CNDMASK_B32_e64,
18620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_U32_e32,
18633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_U32_e64,
18660 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_AND_B32,
18678 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e32,
18702 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_AND_B32,
18720 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e32,
18746 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B32_e32,
18750 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
18755 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_AND_B32_e64,
18760 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
18765 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
18785 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_AND_B32,
18803 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e32,
18838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
18855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
18872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F16_e64,
18900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
18917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
18934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e64,
18958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
18975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
19008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F16_e64,
19026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F16_e64,
19051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e64,
19068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e64,
19093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
19110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
19143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F16_e64,
19161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F16_e64,
19186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e64,
19203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e64,
19228 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
19245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
19278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F16_e64,
19296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F16_e64,
19321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e64,
19338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e64,
19363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
19380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
19413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F16_e64,
19431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F16_e64,
19456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e64,
19473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e64,
19498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
19515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
19766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BCNT_U32_B32_e64,
19814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CEIL_F16_e64,
19832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CEIL_F32_e64,
19851 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CEIL_F64_e64,
19877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SQRT_F16_e64,
19895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SQRT_F32_e64,
19913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SQRT_F64_e64,
19939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FLOOR_F16_e64,
19957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FLOOR_F32_e64,
19982 GIR_BuildMI, /*InsnID*/5, /*Opcode*/AMDGPU::V_CMP_CLASS_F64_e64,
19988 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B64_PSEUDO,
19992 GIR_BuildMI, /*InsnID*/3, /*Opcode*/AMDGPU::V_FRACT_F64_e64,
19999 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_MIN_F64,
20008 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CNDMASK_B64_PSEUDO,
20014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
20031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FLOOR_F64_e64,
20059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RNDNE_F16_e64,
20077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RNDNE_F32_e64,
20096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_RNDNE_F64_e64,
20125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN,
20145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN,
20171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN,
20191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN,
gen/lib/Target/ARM/ARMGenGlobalISel.inc 905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
1001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
1025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
1049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
1073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
1109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
1947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
1967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1987 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
2027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
2075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
2249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2605 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
2661 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
2663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi32,
2696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
2870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
3115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3226 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
3282 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi16,
3317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3479 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi8,
3524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
3547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
3570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
3593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
3616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
3639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
3663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
3681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
3699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
3723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
3751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
3767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
3799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
3823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
3843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
3863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
3879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
3909 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
3925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
3957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
3982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
4027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
4048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
4065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
4083 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi32,
4116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
4132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
4164 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
4189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4212 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
4234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
4255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
4272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
4290 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi16,
4323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
4341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
4359 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi8,
4409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
4438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
4455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
4473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
4491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
4514 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
4535 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
4557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
4575 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULt1i32,
4601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
4623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
4641 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULt1i16,
4668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
4686 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULt1i8,
4716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
4733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
4758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
4775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
4816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
4873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
4890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
4924 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
4941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
5220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
5244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
5268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
5286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTB,
5302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTH,
5323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDri,
5346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDri,
5369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BFC,
5391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BFC,
5408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDrr,
5426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDrr,
5450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
5472 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5499 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5503 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5507 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
5552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5581 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5585 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5589 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5616 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5643 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5647 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5651 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5678 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
5740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
5780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
5820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
5860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
5899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5940 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVTi16,
7089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVTi16,
7111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRri,
7134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRri,
7152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRrr,
7170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRrr,
7194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
7216 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7243 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7251 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
7296 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7298 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7325 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7329 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7333 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7360 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7387 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7391 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7395 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
7487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
7504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNr,
7521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVNr,
7543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORri,
7566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORri,
7584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORrr,
7602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORrr,
7626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
7648 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7675 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7679 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7683 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
7691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
7728 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7757 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7761 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7765 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
7773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7792 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7819 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7823 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7827 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
7835 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7854 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
7888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7924 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
7985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVRS,
8035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVSR,
8055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
8303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
8385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
8633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
8697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
8715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8915 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
8931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
8947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
8963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8995 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
9043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9212 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9232 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9252 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9292 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
9312 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9314 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9332 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
9352 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9372 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9374 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
9392 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
9413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
9661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
9743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
9959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
9975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
9991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
10071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10260 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10280 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10300 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10320 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
10340 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10360 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10380 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10382 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10400 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
10420 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
10441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
10541 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
10557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
10573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
10589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
10605 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
10623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
10871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
10951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11120 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11140 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11160 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11180 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11200 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11220 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
11260 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11280 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11300 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
11421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
11437 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
11485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
11501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11586 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
11606 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
11626 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
11646 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
11666 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11686 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
11713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
11732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
11751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNH,
11767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNS,
11783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTND,
11799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRD,
11817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRS,
11835 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRD,
11853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRS,
11871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i8,
11889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i16,
11907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv2i32,
11925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv16i8,
11943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i16,
11961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i32,
11979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i8,
11997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i16,
12015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv2i32,
12033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv16i8,
12051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i16,
12069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i32,
12087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEd,
12105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEq,
12123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfd,
12141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfq,
12159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhd,
12177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhq,
12195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEd,
12213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEq,
12231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfd,
12249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfq,
12267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhd,
12285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhq,
12303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i8,
12321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i16,
12339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv2i32,
12357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv16i8,
12375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i16,
12393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i32,
12411 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i8,
12429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i16,
12447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv2i32,
12465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv16i8,
12483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i16,
12501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i32,
12519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i8,
12537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i16,
12555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv2i32,
12573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv16i8,
12591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i16,
12609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i32,
12627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv8i8,
12645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv4i16,
12663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv2i32,
12681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv8i8,
12699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv4i16,
12717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv2i32,
12735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv8i8,
12753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv4i16,
12771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv2i32,
12789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDf,
12805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQf,
12821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDf,
12837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQf,
12853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDh,
12869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQh,
12885 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDh,
12901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQh,
12917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDf,
12933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQf,
12949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDf,
12965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQf,
12981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDh,
12997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQh,
13013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDh,
13029 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQh,
13045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDf,
13061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQf,
13077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDf,
13093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQf,
13109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDh,
13125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQh,
13141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDh,
13157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQh,
13173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDf,
13189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQf,
13205 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDf,
13221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQf,
13237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDh,
13253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQh,
13269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDh,
13285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQh,
13301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2h,
13319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2f,
13337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDf,
13353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQf,
13369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDh,
13385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQh,
13401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDf,
13417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQf,
13433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDh,
13449 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQh,
13465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDf,
13481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQf,
13497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDh,
13513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQh,
13529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDf,
13545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQf,
13561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDh,
13577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQh,
13593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDf,
13609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQf,
13625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDh,
13641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQh,
13657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDf,
13673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQf,
13689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDh,
13705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQh,
13721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESIMC,
13737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESMC,
13753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTB16,
13772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTB16,
13791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP8,
13809 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP16,
13827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP32,
13851 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB16,
13881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
13911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
13941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
13971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
14001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
14031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
14061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
14090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
14119 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
14149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
14179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
14209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
14239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i16,
14269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv2i32,
14299 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv8i16,
14329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i32,
14359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
14389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
14419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv4i32,
14449 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv2i64,
14479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
14508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
14537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
14566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
14592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT,
14619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT16,
14645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT,
14672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT16,
14697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsd,
14722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xud,
14747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fd,
14772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fd,
14797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsd,
14822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xud,
14847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hd,
14872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hd,
14897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsq,
14922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xuq,
14947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fq,
14972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fq,
14997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsq,
15022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xuq,
15047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hq,
15072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hq,
15093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD8,
15114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD16,
15135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB16,
15156 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB8,
15177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
15198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
15219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD16,
15240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD8,
15261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB16,
15282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB8,
15303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QASX,
15324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSAX,
15345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQASX,
15366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSAX,
15387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHASX,
15408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD16,
15429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD8,
15450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSAX,
15471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB16,
15492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB8,
15513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHASX,
15534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD16,
15555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD8,
15576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSAX,
15597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB16,
15618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB8,
15639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAD8,
15660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32B,
15679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CB,
15698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32H,
15717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CH,
15736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32W,
15755 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CW,
15774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD16,
15795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD8,
15816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QASX,
15837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB8,
15858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSAX,
15879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB16,
15900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB8,
15921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD16,
15942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD8,
15963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQASX,
15984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSAX,
16005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB16,
16026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHASX,
16047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD16,
16068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD8,
16089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSAX,
16110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB16,
16131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB8,
16152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHASX,
16173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD16,
16194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD8,
16215 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSAX,
16236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB16,
16257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB8,
16278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAD8,
16299 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUAD,
16320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUADX,
16341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSD,
16362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSDX,
16383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32B,
16402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CB,
16421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32H,
16440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CH,
16459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32W,
16478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CW,
16497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i16,
16518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv2i32,
16539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i16,
16560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i32,
16581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i8,
16602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv16i8,
16623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i16,
16644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv2i32,
16665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i16,
16686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i32,
16707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i8,
16728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv16i8,
16749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i16,
16770 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv2i32,
16791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i16,
16812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i32,
16833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i8,
16854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv16i8,
16875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i16,
16896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv2i32,
16917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i16,
16938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i32,
16959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i8,
16980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv16i8,
17001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i16,
17022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i32,
17043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i16,
17064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i32,
17085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i8,
17106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv16i8,
17127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv1i64,
17148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i64,
17169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i16,
17190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i32,
17211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i16,
17232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i32,
17253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i8,
17274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv16i8,
17295 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv1i64,
17316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i64,
17337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv8i8,
17358 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv4i16,
17379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv2i32,
17400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpd,
17421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpq,
17442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i16,
17463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv2i32,
17484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv8i16,
17505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i32,
17526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i16,
17547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv2i32,
17568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv8i16,
17589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i32,
17610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp8,
17631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp64,
17650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv4i32,
17671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv2i64,
17692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i16,
17713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv2i32,
17734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i16,
17755 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i32,
17776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i8,
17797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv16i8,
17818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i16,
17839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv2i32,
17860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i16,
17881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i32,
17902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i8,
17923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv16i8,
17944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i16,
17965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i32,
17986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i16,
18007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i32,
18028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i8,
18049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv16i8,
18070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv1i64,
18091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i64,
18112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i16,
18133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i32,
18154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i16,
18175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i32,
18196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i8,
18217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv16i8,
18238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv1i64,
18259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i64,
18280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv8i8,
18301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv4i16,
18322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv2i32,
18343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfd,
18364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfq,
18385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhd,
18406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhq,
18427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfd,
18448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfq,
18469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThd,
18490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThq,
18511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i16,
18532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv2i32,
18553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i16,
18574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i32,
18595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i8,
18616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv16i8,
18637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i16,
18658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv2i32,
18679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i16,
18700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i32,
18721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i8,
18742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv16i8,
18763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfd,
18784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfq,
18805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhd,
18826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhq,
18847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi8,
18868 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi16,
18889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi32,
18910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDf,
18931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDh,
18952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i8,
18973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i16,
18994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv2i32,
19015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv16i8,
19036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i16,
19057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i32,
19078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i8,
19099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i16,
19120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv2i32,
19141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv16i8,
19162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i16,
19183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i32,
19204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs8,
19225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs16,
19246 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs32,
19267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu8,
19288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu16,
19309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu32,
19330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXf,
19351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXh,
19372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs8,
19393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs16,
19414 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs32,
19435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu8,
19456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu16,
19477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu32,
19498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINf,
19519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINh,
19540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfd,
19561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfq,
19582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShd,
19603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShq,
19624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfd,
19645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfq,
19666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShd,
19687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShq,
19708 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i16,
19729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i32,
19750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i16,
19771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i32,
19792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i8,
19813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv16i8,
19834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv1i64,
19855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i64,
19876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i16,
19897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i32,
19918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i16,
19939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i32,
19960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i8,
19981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv16i8,
20002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv1i64,
20023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i64,
20044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i16,
20065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i32,
20086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i16,
20107 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i32,
20128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i8,
20149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv16i8,
20170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv1i64,
20191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i64,
20212 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i16,
20233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i32,
20254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i16,
20275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i32,
20296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i8,
20317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv16i8,
20338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv1i64,
20359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i64,
20380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i16,
20401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i32,
20422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i16,
20443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i32,
20464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i8,
20485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv16i8,
20506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv1i64,
20527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i64,
20548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i16,
20569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i32,
20590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i16,
20611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i32,
20632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i8,
20653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv16i8,
20674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv1i64,
20695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i64,
20716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i16,
20737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i32,
20758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i16,
20779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i32,
20800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i8,
20821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv16i8,
20842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv1i64,
20863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i64,
20884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i16,
20905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i32,
20926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i16,
20947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i32,
20968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i8,
20989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv16i8,
21010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv1i64,
21031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i64,
21052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESD,
21071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESE,
21090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU1,
21109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU0,
21128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs16,
21149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs32,
21170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs8,
21191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu16,
21212 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu32,
21233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu8,
21254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs16,
21275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs32,
21296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs8,
21317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu16,
21338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu32,
21359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu8,
21380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTAB16,
21402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB16,
21424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUAD,
21445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUADX,
21466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSD,
21487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSDX,
21508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBB,
21529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBT,
21550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTB,
21571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
21592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWB,
21613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWT,
21634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTAB16,
21656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD,
21677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB,
21698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBB,
21719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBT,
21740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTB,
21761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
21782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWB,
21803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWT,
21830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32bh,
21853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32th,
21876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USADA8,
21900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USADA8,
21924 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAD,
21948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLADX,
21972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSD,
21996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSDX,
22020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTD,
22042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTD,
22064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTQ,
22086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTQ,
22108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX1,
22132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU0,
22154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H,
22176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H2,
22198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU1,
22220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAD,
22244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLADX,
22268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSD,
22292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSDX,
22316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABB,
22340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABT,
22364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATB,
22388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
22412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWB,
22436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWT,
22460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABB,
22484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABT,
22508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATB,
22532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
22556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWB,
22580 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWT,
22604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22796 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22843 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
22847 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
22854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1C,
22875 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
22879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
22886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1M,
22907 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
22911 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
22918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1P,
22943 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
22950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX2,
22974 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
22977 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
22988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL3Pseudo,
23016 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23019 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
23030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX3Pseudo,
23054 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
23065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL4Pseudo,
23092 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
23103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX4Pseudo,
23122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLREX,
23132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLREX,
23151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t__brkdiv0,
23169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::HINT,
23190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DBG,
23211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDF,
23230 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DMB,
23249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DSB,
23268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ISB,
23287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tHINT,
23308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUDF,
23327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDF,
23346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DMB,
23367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DSB,
23388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ISB,
23409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2HINT,
23430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DBG,
23446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMRS,
23462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DoLoopStart,
23476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMSR,
23499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SPACE,
23519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SEL,
23541 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SASX,
23563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD16,
23585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD8,
23607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSAX,
23629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB16,
23651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB8,
23673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UASX,
23695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD16,
23717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD8,
23739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAX,
23761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB16,
23783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB8,
23805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SEL,
23827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SASX,
23849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD16,
23871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD8,
23893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSAX,
23915 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB16,
23937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB8,
23959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UASX,
23981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD16,
24003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD8,
24025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAX,
24047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB16,
24069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB8,
24099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR,
24127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR2,
24153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR,
24181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR2,
24215 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP,
24246 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP2,
24275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP,
24306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP2,
24337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR,
24368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR2,
24397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR,
24428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR2,
24458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
24476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
24494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
24522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv2i32,
24540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r,
24560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv4i16,
24578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r,
24598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv8i8,
24616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r,
24641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi,
24659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi,
24677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi16,
24694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi32imm,
24709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi16,
24725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi32imm,
24748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTS,
24767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTD,
24792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv2i64,
24810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv4i32,
24828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv8i16,
24862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv2i64,
24885 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv2i64,
24900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
24929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv4i32,
24952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32,
24967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
24996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv8i16,
25019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16,
25034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
25065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLri,
25081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLrr,
25106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSRrr,
25134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
25154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREVSH,
25175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
25190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ASRrr,
25218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMUL,
25235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMUL,
25267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDH,
25288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDS,
25309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDD,
25330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfd,
25358 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
25381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
25398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhd,
25422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfq,
25440 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf32,
25473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
25497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
25515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhq,
25533 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25535 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf16,
25570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBH,
25591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBS,
25612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBD,
25633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfd,
25661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShd,
25683 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShd,
25699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhd,
25723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfq,
25741 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf32,
25774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShq,
25798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShq,
25816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhq,
25834 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf16,
25871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULH,
25897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
25917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
25933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULS,
25961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
25981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
25997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULD,
26020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfd,
26041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhd,
26063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfq,
26081 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf32,
26108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhq,
26126 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf16,
26165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAH,
26198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
26220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
26242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
26264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
26282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAS,
26317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
26339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
26361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
26383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
26401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAD,
26432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
26450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfd,
26476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
26505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
26523 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfq,
26549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
26578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVH,
26599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVS,
26620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVD,
26657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULH,
26672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGH,
26705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
26733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
26757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
26779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
26794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGS,
26827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
26855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
26879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
26901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
26916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGD,
26936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGfd,
26954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhd,
26973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGf32q,
26989 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VNEGf32,
27013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhq,
27029 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VNEGf16,
27059 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHS,
27081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTDS,
27098 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHD,
27127 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBSH,
27133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27148 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBDH,
27154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTSD,
27204 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSH,
27208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27227 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSS,
27231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27250 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSD,
27254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27273 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSH,
27277 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27296 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSS,
27300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27319 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSD,
27323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27338 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZD,
27344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27359 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZS,
27365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27380 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZH,
27386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sd,
27420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
27440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sd,
27459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sq,
27475 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32z,
27498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
27519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sq,
27535 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16z,
27574 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUH,
27578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27597 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUS,
27601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27620 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUD,
27624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27643 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUH,
27647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27666 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUS,
27670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27689 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUD,
27693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27708 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZD,
27714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27729 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZS,
27735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27750 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZH,
27756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2ud,
27790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
27810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2ud,
27829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2uq,
27845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32z,
27868 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
27889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2uq,
27905 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16z,
27940 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOH,
27963 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOS,
27986 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOD,
28008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fd,
28026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hd,
28045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fq,
28061 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32s32n,
28085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hq,
28101 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16s16n,
28136 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
28140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOH,
28159 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
28163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOS,
28182 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
28186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOD,
28204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fd,
28222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hd,
28241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fq,
28257 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32u32n,
28281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hq,
28297 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28299 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16u16n,
28331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSH,
28349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSS,
28367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSD,
28385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfd,
28403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShd,
28422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfq,
28438 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABSf32,
28462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShq,
28478 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABSf16,
28602 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf32,
28641 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf16,
28766 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf32,
28805 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf16,
28841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv2i32,
28862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i16,
28884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i32,
28902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs32,
28928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i8,
28950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i16,
28968 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs16,
28995 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv16i8,
29013 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs8,
29049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv2i32,
29070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i16,
29092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i32,
29110 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs32,
29136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i8,
29158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i16,
29176 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs16,
29203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv16i8,
29221 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs8,
29257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv2i32,
29278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i16,
29300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i32,
29318 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu32,
29344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i8,
29366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i16,
29384 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu16,
29411 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv16i8,
29429 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu8,
29465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv2i32,
29486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i16,
29508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i32,
29526 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu32,
29552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i8,
29574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i16,
29592 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu16,
29619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv16i8,
29637 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu8,
29670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tB,
29682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2B,
29711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLZ,
29726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLZ,
29746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv2i32,
29764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i16,
29783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i32,
29799 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs32,
29822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i8,
29841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i16,
29857 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs16,
29881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv16i8,
29897 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs8,
29926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTd,
29944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTq,
29970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REV,
29985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREV,
30000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REV,
30021 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
30043 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
30073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RBIT,
30088 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RBIT,
30110 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30112 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
30119 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
30141 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30143 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
30150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
30172 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30174 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
30181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR8,
30250 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32P,
30272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16P,
30300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTH,
30318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTS,
30336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTD,
30403 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32M,
30425 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16M,
30455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXH,
30473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXS,
30491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXD,
30510 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32X,
30532 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16X,
30560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRH,
30578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRS,
30596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRD,
gen/lib/Target/Mips/MipsGenGlobalISel.inc 737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
1046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
1067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
1106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
2146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2546 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
3131 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3135 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3140 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3144 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3166 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3170 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3175 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3179 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3199 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3203 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3223 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3227 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3251 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3271 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3275 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3295 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3319 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3323 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3343 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3347 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3367 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3371 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3538 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3542 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3562 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3566 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3586 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3590 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3610 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3614 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3634 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3638 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3658 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3662 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3682 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3686 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3706 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3730 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3734 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3754 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3850 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3854 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3874 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3898 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3922 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3926 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3946 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3950 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3970 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3974 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3994 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3998 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4018 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4022 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4042 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4046 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4066 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4070 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4152 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4156 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4176 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4180 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4200 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4204 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4224 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4228 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4250 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4254 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4259 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4263 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4285 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4289 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4294 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4298 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4535 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4551 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4615 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
4759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
4775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
4791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
4807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
4823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D,
4839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W,
4855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D,
4871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W,
4887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D,
4903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W,
4919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D,
4935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W,
4951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D,
4967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W,
4983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D,
4999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B,
5015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H,
5031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W,
5047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D,
5063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM,
5079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM,
5095 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM,
5111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM,
5127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM,
5143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM,
5159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM,
5175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM,
5191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM,
5207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM,
5223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM,
5239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM,
5255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM,
5271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM,
5298 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH,
5322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W,
5346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB,
5370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM,
5394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM,
5418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2,
5437 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B,
5456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H,
5475 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W,
5494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D,
5513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B,
5532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H,
5551 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W,
5570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D,
5589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B,
5608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H,
5627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W,
5646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D,
5665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B,
5684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H,
5703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W,
5722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D,
5745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH,
5768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH,
5791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB,
5814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB,
5833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB,
5852 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB,
5871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH,
5890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH,
5909 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB,
5928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH,
5947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W,
5966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB,
5985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH,
6004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH,
6023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W,
6042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH,
6061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB,
6080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB,
6099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB,
6118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB,
6137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH,
6156 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH,
6175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH,
6194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH,
6213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W,
6232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W,
6251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W,
6270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W,
6289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB,
6308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB,
6327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH,
6346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B,
6365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H,
6384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W,
6403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D,
6422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B,
6441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H,
6460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W,
6479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D,
6498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B,
6517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H,
6536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W,
6555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D,
6574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B,
6593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H,
6612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W,
6631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D,
6650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B,
6669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H,
6688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W,
6707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D,
6726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B,
6745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H,
6764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W,
6783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D,
6802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B,
6821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H,
6840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W,
6859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D,
6878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B,
6897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H,
6916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W,
6935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D,
6954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B,
6973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H,
6992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W,
7011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D,
7030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B,
7049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H,
7068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W,
7087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D,
7106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H,
7125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W,
7144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D,
7163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H,
7182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W,
7201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D,
7220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W,
7239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D,
7258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H,
7277 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W,
7296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W,
7315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D,
7334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W,
7353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D,
7372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W,
7391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D,
7410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W,
7429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D,
7448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W,
7467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D,
7486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W,
7505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D,
7524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W,
7543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D,
7562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W,
7581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D,
7600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W,
7619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D,
7638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W,
7657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D,
7676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W,
7695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D,
7714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W,
7733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D,
7752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W,
7771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D,
7790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W,
7809 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D,
7828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W,
7847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D,
7866 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H,
7885 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W,
7904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H,
7923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W,
7942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D,
7961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H,
7980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W,
7999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D,
8018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H,
8037 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W,
8056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D,
8075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H,
8094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W,
8113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D,
8132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B,
8151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H,
8170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W,
8189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D,
8208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B,
8227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H,
8246 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W,
8265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D,
8284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H,
8303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W,
8322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H,
8341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W,
8360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B,
8379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H,
8398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W,
8417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D,
8436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B,
8455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H,
8474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W,
8493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D,
8512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B,
8531 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H,
8550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W,
8569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D,
8588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B,
8607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H,
8626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W,
8645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D,
8664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B,
8683 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H,
8702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W,
8721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D,
8740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B,
8759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H,
8778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W,
8797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D,
8816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM,
8835 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM,
8854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM,
8873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM,
8892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM,
8911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM,
8930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM,
8949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM,
8968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM,
8987 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM,
9006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM,
9025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM,
9044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2,
9063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2,
9082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2,
9101 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2,
9120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2,
9139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2,
9158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2,
9177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2,
9196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2,
9215 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2,
9234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2,
9253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2,
9272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2,
9291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2,
9310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2,
9327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH,
9344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH,
9361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB,
9378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB,
9408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2,
9430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W,
9452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W,
9474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND,
9496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN,
9518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND,
9540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B,
9562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H,
9584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W,
9606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D,
9628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2,
9650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2,
9672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2,
9694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2,
9716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B,
9738 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H,
9760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W,
9782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D,
9804 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B,
9826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H,
9848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W,
9870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D,
9892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H,
9914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W,
9936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D,
9958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H,
9980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W,
10002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D,
10024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H,
10046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W,
10068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D,
10090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H,
10112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W,
10134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D,
10156 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H,
10178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W,
10200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H,
10222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W,
10244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H,
10266 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W,
10288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H,
10310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W,
10332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B,
10354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H,
10376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W,
10398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D,
10418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO,
10436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP,
10453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP_MM,
10470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP,
10487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP_MM,
10504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH,
10521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W,
10538 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB,
10555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM,
10572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM,
10589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2,
10606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB,
10623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB,
10640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB,
10657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH,
10674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH,
10691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH,
10708 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM,
10725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM,
10742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM,
10759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM,
10776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM,
10793 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM,
10821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH,
10846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W,
10871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM,
10896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM,
10920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH,
10943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB,
10962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W,
10982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W,
11002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W,
11022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH,
11042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB,
11062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH,
11082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH,
11102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W,
11122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL,
11142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR,
11162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL,
11182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR,
11202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH,
11222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB,
11242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB,
11262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB,
11282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB,
11302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH,
11322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV,
11342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH,
11362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH,
11382 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH,
11402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH,
11422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB,
11442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB,
11462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB,
11482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH,
11502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W,
11522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W,
11542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH,
11562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH,
11582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM,
11602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM,
11622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM,
11642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM,
11662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM,
11682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM,
11702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM,
11722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM,
11742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM,
11762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM,
11782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM,
11802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM,
11822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM,
11842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM,
11862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM,
11882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM,
11902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM,
11922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM,
11942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM,
11962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2,
11982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2,
12002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2,
12022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2,
12042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2,
12062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2,
12082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2,
12102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2,
12122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2,
12142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2,
12162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2,
12182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2,
12200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH,
12218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC,
12236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC,
12258 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12283 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
12308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM,
12322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32,
12355 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRA,
12360 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12391 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRL,
12396 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12427 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL,
12432 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12458 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::ADDu,
12463 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12489 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRAV,
12494 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12520 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRLV,
12525 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12552 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MUL_R6,
12557 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12584 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIV,
12589 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12615 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLLV,
12620 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12647 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MOD,
12652 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12678 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SUBu,
12683 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12710 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIVU,
12715 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12742 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MODU,
12747 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEQ,
12812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SNE,
12827 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32,
12831 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
12843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32,
12881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
12901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16,
12921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM,
12941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM,
13001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL,
13019 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV,
13130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL,
13150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16,
13170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM,
13190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM,
13250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
13268 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV,
13379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA,
13399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16,
13419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM,
13479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA,
13497 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV,
13602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu,
13618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
13641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64,
13657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
13684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16,
13703 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
13707 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltiCCRxImmX16,
13712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
13729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM,
13746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
13763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
13780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
13803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64,
13819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
13846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM,
13862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
13879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
13884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu,
13901 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
13906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
13923 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
13928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
13945 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
13950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
13966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
13982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
13999 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
14004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14021 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
14026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14050 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
14055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64,
14072 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
14077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
14094 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
14099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14116 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
14121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64,
14153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
14170 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
14175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14192 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
14197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14222 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XorRxRxRy16,
14227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16,
14246 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
14250 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16,
14255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
14272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16,
14291 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImm16,
14295 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16,
14300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
14317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16,
14336 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::XorRxRxRy16,
14341 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::LiRxImmX16,
14345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
14364 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
14368 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16,
14373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
14390 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
14409 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
14413 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16,
14418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
14435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
14453 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
14458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM,
14476 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
14481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
14499 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
14504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
14522 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
14527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
14544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM,
14561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
14579 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
14584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
14602 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
14607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
14638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S,
14654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S,
14670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S,
14686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S,
14702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S,
14718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S,
14734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S,
14757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D,
14773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D,
14789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D,
14805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D,
14821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D,
14837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D,
14853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D,
14880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S_MMR6,
14896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S_MMR6,
14912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S_MMR6,
14928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S_MMR6,
14944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S_MMR6,
14960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S_MMR6,
14976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S_MMR6,
14999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D_MMR6,
15015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D_MMR6,
15031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D_MMR6,
15047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D_MMR6,
15063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D_MMR6,
15079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D_MMR6,
15095 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D_MMR6,
15121 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S,
15126 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
15141 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S,
15146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
15161 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S,
15166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
15188 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D,
15193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
15208 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D,
15213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
15228 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D,
15233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
15259 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S_MMR6,
15264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
15279 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S_MMR6,
15284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
15299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S_MMR6,
15304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
15326 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D_MMR6,
15331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
15346 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D_MMR6,
15351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
15366 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D_MMR6,
15371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
15410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
15438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
15466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I,
15494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
15522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
15550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
15578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S,
15606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
15634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBeqZ,
15662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
15690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
15718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
15746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
15774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
15802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
15830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
15859 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
15864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
15893 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
15898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
15927 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
15932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
15961 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
15966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
15995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
16000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
16029 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
16034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
16063 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
16068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
16097 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
16102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
16131 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
16136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
16165 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
16170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
16199 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
16204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I,
16233 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
16238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
16267 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
16272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16301 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
16306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16335 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
16340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16369 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
16374 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16403 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
16408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16437 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
16442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
16471 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
16476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16505 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
16510 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16539 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
16544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16573 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
16578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
16607 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
16612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S,
16641 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
16646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
16674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt,
16703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSlt,
16732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu,
16761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSltu,
16790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt,
16819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu,
16848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZCmp,
16877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZCmp,
16907 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
16912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
16941 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
16946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
16975 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
16980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17009 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17043 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17077 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17111 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
17116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17145 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17179 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
17184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17213 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17247 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17281 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17315 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
17320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
17349 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
17383 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
17388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
17417 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
17451 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
17485 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
17540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S,
17560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6,
17580 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
17600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
17620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
17640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
17660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
17680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
17739 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ,
17744 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ,
17749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR,
17767 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6,
17772 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6,
17777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM,
17806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
17834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64,
17862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
17890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
17918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
17946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
17974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64,
18030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
18058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
18086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
18114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
18143 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18177 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18211 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18245 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18279 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18313 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18347 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18381 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18415 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
18449 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64,
18483 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
18517 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
18551 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
18585 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
18619 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
18653 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
18687 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
18721 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
18755 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18789 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18823 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18857 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18891 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18925 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18959 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
18993 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
19027 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
19032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
19061 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
19066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64,
19095 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
19100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
19129 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
19134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
19163 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
19197 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
19231 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
19265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
19299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
19333 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
19403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
19423 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
19443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
19463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
19483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
19503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
19522 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64,
19527 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
19532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
19552 GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32,
19556 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64,
19561 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32,
19565 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
19570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
19698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
19719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
19754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6,
19782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
19804 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
19826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
19848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
19921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
19943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
19983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
20005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
20053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S,
20088 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6,
20116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32,
20138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64,
20211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D,
20251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W,
20309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6,
20386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
20404 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
20440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
20458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
20554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6,
20737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
20763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
20789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
20815 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
20841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S,
20867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM,
20927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
20954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
20981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
21008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
21035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
21062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
21089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32,
21116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64,
21143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM,
21980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO,
21998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_R6,
22016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_MM,
22068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO,
22086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO_R6,
22270 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH,
22274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR,
22287 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM,
22291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM,
22311 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH,
22315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
734 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
753 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
831 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
1009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
1051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
1240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
1270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
1300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
1330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
1360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1390 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1510 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
1630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
1660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
1690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
1720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
1750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
1780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
1811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
1880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
1899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
1918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
1937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
1975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
2108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
2127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
2146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2701 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2796 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2815 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2835 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
2872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
2930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
2989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
3019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
3037 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
3055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
3073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
3091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
3110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
3129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
3160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
3189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
3219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
3237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
3255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
3274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
3311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
3458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
3476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3530 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
3568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
3599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
3676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
3752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
3780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
3808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
3836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
3864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
3892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
3920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
3937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
3954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
3971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
3988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
4005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
4022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
4039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
4074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
4102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
4130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
4220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
4237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
5240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
5266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
5292 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
5318 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
5344 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
5370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
5396 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
5422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
5448 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
5474 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
5500 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D,
5526 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5531 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D,
5552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
5578 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
5604 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
5630 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
5656 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
5682 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
5708 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
5734 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
5766 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
5792 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
5818 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
5844 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
5870 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
5896 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D,
5922 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
5948 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
5974 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
6000 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
6005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
9311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
9389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
9403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
9487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
9512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
9525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
9544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
9580 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL,
9603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL,
9620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
9637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
9685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL,
9702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
9748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL,
9771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL,
9788 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
9805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
9853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL,
9870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
9916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA,
9939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA,
9956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
9973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
10021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA,
10038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
10075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
10160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
10180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10221 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
10226 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10247 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
10252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10273 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
10278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
10304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
10334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
10349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10380 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
10385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10401 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
10406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
10427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10443 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
10448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10494 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10515 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10536 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10541 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10557 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
10592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
10608 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
10613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10629 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
10634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10650 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
10655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10671 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
10676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
10754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10775 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
10780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10801 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
10806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
10836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10852 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
10857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10873 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
10878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10909 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10930 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
10966 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
10971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
10987 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
10992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
11023 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
11028 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S,
11033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11054 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
11059 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S,
11064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11086 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S,
11091 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
11096 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11101 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11123 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S,
11128 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
11133 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11159 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
11164 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D,
11169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11190 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
11195 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D,
11200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11222 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D,
11227 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
11232 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11259 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D,
11264 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
11269 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11297 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
11302 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S,
11307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11329 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S,
11334 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
11339 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11365 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
11370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D,
11375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11397 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D,
11402 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
11407 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
11567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
11592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
11613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
11634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
11655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
11676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
11697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
11718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
11752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
11777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
11802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
11823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
11844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
11865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
11886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
11907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
11928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
11967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
11979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
11991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
12015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D,
12027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D,
12039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D,
12051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D,
12071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D,
12083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D,
12109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D,
12121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D,
12133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D,
12145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D,
12165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D,
12177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D,
12240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L,
12258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L,
12275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L,
12336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU,
12354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU,
12371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU,
12406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
12418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
12430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
12450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
12462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
12474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
gen/lib/Target/X86/X86GenGlobalISel.inc 864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC8r,
876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC8r,
891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri,
921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC16r,
946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC16r,
962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri8,
978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri,
1008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
1021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC32r,
1033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC32r,
1049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri8,
1065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri,
1095 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1107 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
1120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC64r,
1132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC64r,
1148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri8,
1165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri32,
1242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB8ri,
1678 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
1694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri,
1729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
1745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri,
1780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
2184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri8,
2200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri,
2235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri8,
2251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri,
2286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri8,
2303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri32,
2582 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2586 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2590 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2616 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2620 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2624 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2644 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2648 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2652 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
2657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND8ri,
2716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri8,
2732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri,
2775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
2898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
2919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
2940 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
2961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
2982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
2997 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr16,
3017 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr8,
3041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri8,
3060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri,
3082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri8,
3396 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri32,
3418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3475 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3479 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3483 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3548 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3552 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3556 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3671 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3675 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3679 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4038 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4042 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4046 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
4051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR8ri,
4111 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4114 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
4122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS16rr,
4143 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4146 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
4154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS16rr,
4172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri8,
4189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri,
4233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
4260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
4287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4314 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
4341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
4368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4432 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4435 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
4443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS32rr,
4465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4507 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4529 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4532 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
4540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS32rr,
4562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri8,
4600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri,
4646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4845 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4848 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
4856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS64rr,
4878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4942 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4945 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
4953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS64rr,
4975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri8,
5014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri32,
5049 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5053 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5057 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
5062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5122 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5126 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5130 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
5135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5245 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5249 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5253 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
5258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5619 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5623 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5627 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr,
5632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5653 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5657 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5661 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr,
5666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5687 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5691 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5695 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr,
5700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5715 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5719 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5723 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr,
5728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT8r,
5763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR8ri,
5801 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5804 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
5812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC16rr,
5833 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5836 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
5844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC16rr,
5857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT16r,
5874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR16ri8,
5891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR16ri,
5929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK32rr,
5950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK32rr,
5972 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5975 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
5983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC32rr,
6005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK32rr,
6026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK32rr,
6048 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6051 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
6059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC32rr,
6074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT32r,
6093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR32ri8,
6112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR32ri,
6152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK64rr,
6173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK64rr,
6195 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6198 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
6206 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC64rr,
6228 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK64rr,
6249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK64rr,
6271 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6274 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
6282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC64rr,
6297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT64r,
6316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR64ri8,
6336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR64ri32,
6371 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6375 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6379 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr,
6384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6444 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6448 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6452 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr,
6457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6567 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6571 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6575 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr,
6580 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKBWrr,
6933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKWDrr,
6952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKDQrr,
7138 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7141 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7166 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7169 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
7177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBWDrr,
7239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBDQrr,
7255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBBWrr,
7271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDWQrr,
7287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDWDrr,
7303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUWQrr,
7319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUWDrr,
7335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUDQrr,
7351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBWrr,
7367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBQrr,
7383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBDrr,
7399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDDQrr,
7415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBWrr,
7431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBQrr,
7447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBDrr,
7463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZSSrr,
7479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPSrr,
7495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPSYrr,
7511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZSDrr,
7527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPDrr,
7543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPDYrr,
7559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESIMCrr,
7575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESIMCrr,
7591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RSQRTSSr_Int,
7608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VRSQRTSSr_Int,
7625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RCPSSr_Int,
7642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VRCPSSr_Int,
7665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESKEYGENASSIST128rr,
7684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESKEYGENASSIST128rr,
7703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PDEP32rr,
7722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PDEP64rr,
7741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PEXT32rr,
7760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PEXT64rr,
7779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNBrr,
7798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNWrr,
7817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNDrr,
7836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDSWrr,
7855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBSWrr,
7874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNBYrr,
7893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNWYrr,
7912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNDYrr,
7931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDSWYrr,
7950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBSWYrr,
7969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNBrr,
7988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNWrr,
8007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNDrr,
8026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PHADDSWrr,
8045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PHSUBSWrr,
8064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r8,
8083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r16,
8102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r32,
8121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r64r64,
8140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1NEXTErr,
8159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1MSG1rr,
8178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1MSG2rr,
8197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256MSG1rr,
8216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256MSG2rr,
8235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCrr,
8254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTrr,
8273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECrr,
8292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTrr,
8311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCYrr,
8330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTYrr,
8349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECYrr,
8368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTYrr,
8387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESENCrr,
8406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESENCLASTrr,
8425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESDECrr,
8444 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESDECLASTrr,
8463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::EXTRQ,
8482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INSERTQ,
8501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZ128rr,
8520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZ256rr,
8539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZrr,
8558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZ128rr,
8577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZ256rr,
8596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZrr,
8615 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZ128rr,
8634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZ256rr,
8653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZrr,
8672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZ128rr,
8691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZ256rr,
8710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZrr,
8735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCMPSSrr_Int,
8757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCMPSDrr_Int,
8779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CMPSSrr_Int,
8801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CMPSDrr_Int,
8823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMPSADBWrri,
8845 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPSrri,
8867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPDrri,
8889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPSYrri,
8911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMPSADBWYrri,
8933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MPSADBWrri,
8955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DPPSrri,
8977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DPPDrri,
8999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1RNDS4rri,
9021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PCLMULQDQrr,
9043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQrr,
9065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQYrr,
9087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZrr,
9109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZ128rr,
9131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZ256rr,
9153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMADCSWDrr,
9175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMADCSSWDrr,
9197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
9219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWDrr,
9241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSWWrr,
9263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSWDrr,
9285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDQLrr,
9307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDQHrr,
9329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDDrr,
9351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDQLrr,
9373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDQHrr,
9395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
9417 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256RNDS2rr,
9436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PAUSE,
9447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SFENCE,
9458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LFENCE,
9469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MFENCE,
9480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VZEROALL,
9491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VZEROUPPER,
9502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MMX_EMMS,
9513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::FEMMS,
9524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XEND,
9534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WBINVD,
9545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WBNOINVD,
9555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAVEPREVSSP,
9565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SETSSBSY,
9579 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INT3,
9592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XABORT,
9605 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INT,
9619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFLAGS32,
9633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFLAGS64,
9647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SLWPCB,
9661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SLWPCB64,
9675 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XBEGIN,
9689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFSBASE,
9703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFSBASE64,
9717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDGSBASE,
9731 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDGSBASE64,
9745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDPID32,
9759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFLAGS32,
9773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFLAGS64,
9786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INCSSPD,
9799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INCSSPQ,
9813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFSBASE,
9827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFSBASE64,
9841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRGSBASE,
9855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRGSBASE64,
9869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTWRITEr,
9883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTWRITE64r,
9898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LLWPCB,
9913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LLWPCB64,
9928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR16,
9943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR32,
9958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR64,
9977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDSSPD,
9993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDSSPQ,
10010 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
10013 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MWAITrr,
10037 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LWPVAL32rri,
10057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LWPVAL64rri,
10077 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
10080 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
10083 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MWAITXrrr,
10103 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
10106 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
10109 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XSETBV,
10130 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMASKMOVDQU,
10153 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10156 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMASKMOVDQU64,
10176 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MASKMOVDQU,
10199 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MASKMOVDQU64,
10240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10281 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
10304 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8,
10308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
10325 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr16,
10329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
10346 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
10418 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZ256rr,
10422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZ256rr,
10476 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr,
10480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr,
10508 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr,
10512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZrr,
10594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10715 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVZXWDZrr,
10719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr,
10768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV8ri,
10783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV16ri,
10798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r0,
10811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r1,
10824 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r_1,
10838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32ImmSExti8,
10855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV64ImmSExti8,
10869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV64ri32,
10893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp032,
10907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp132,
10923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp064,
10937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp164,
10952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp080,
10965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp180,
11124 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZ256rr,
11128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZ256rr,
11226 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr,
11230 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr,
11282 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr,
11286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZrr,
11402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVWrk,
11420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVBrk,
11460 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVWrk,
11464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
11486 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVBrk,
11490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
11507 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8,
11511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
11528 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr16,
11532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
11549 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOV32rr,
11553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
11721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8rr,
11737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL8ri,
11749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL8rCL,
11772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16rr,
11788 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL16ri,
11800 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL16rCL,
11823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32rr,
11839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL32ri,
11854 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11857 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
11865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLX32rr,
11877 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL32rCL,
11900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64rr,
11916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL64ri,
11931 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11934 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
11942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLX64rr,
11954 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL64rCL,
11985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8r1,
12000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8ri,
12012 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8rCL,
12035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16r1,
12050 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16ri,
12062 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16rCL,
12085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32r1,
12100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32ri,
12115 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12118 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12126 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRX32rr,
12138 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32rCL,
12161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64r1,
12176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64ri,
12191 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12194 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRX64rr,
12214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64rCL,
12245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8r1,
12260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8ri,
12272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8rCL,
12295 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16r1,
12310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16ri,
12322 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16rCL,
12345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32r1,
12360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32ri,
12375 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12378 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SARX32rr,
12398 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32rCL,
12421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64r1,
12436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64ri,
12451 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12454 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SARX64rr,
12474 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64rCL,
13970 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSS2SDrr,
13988 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSS2SDZrr,
14115 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSD2SSrr,
14134 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSD2SSZrr,
14451 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SSrr,
14470 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SSrr,
14489 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SSZrr,
14508 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SSZrr,
14551 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SDrr,
14570 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SDrr,
14589 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SDZrr,
14608 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SDZrr,
14807 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI2SSZrr,
14826 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI642SSZrr,
14847 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14850 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI2SDZrr,
14866 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
14869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI642SDZrr,
16635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL16ri,
16815 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSr,
16833 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSZr,
16879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDr,
16897 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDZr,
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 760 case GIR_BuildMI: {