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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/GlobalISel/CallLowering.cpp 300 MVT VAVT = VA.getValVT();
lib/Target/AArch64/AArch64FastISel.cpp 3172 MVT CopyVT = RVLocs[0].getValVT();
3910 MVT DestVT = VA.getValVT();
lib/Target/AArch64/AArch64ISelLowering.cpp 3240 assert(VA.getValVT().isScalableVector() &&
3244 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
3253 ArgValue = DAG.getZExtOrTrunc(ArgValue, DL, VA.getValVT());
3259 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
3273 MVT MemVT = VA.getValVT();
3283 assert(VA.getValVT().isScalableVector() &&
3522 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3531 Val = DAG.getZExtOrTrunc(Val, DL, VA.getValVT());
3887 assert(VA.getValVT() == MVT::i32 && "only expect 32 -> 64 upper bits");
3902 assert(VA.getValVT().isScalableVector() &&
3953 : VA.getValVT().getSizeInBits();
3999 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3999 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
4000 VA.getValVT() == MVT::i16)
4001 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
4206 assert(VA.getValVT() == MVT::i32 && "only expect 32 -> 64 upper bits");
lib/Target/AMDGPU/SIISelLowering.cpp 1516 unsigned ArgSize = VA.getValVT().getStoreSize();
1526 MVT MemVT = VA.getValVT();
2168 EVT ValVT = VA.getValVT();
2399 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2403 DAG.getValueType(VA.getValVT()));
2404 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2408 DAG.getValueType(VA.getValVT()));
2409 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2412 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2828 Flags.getByValSize() : VA.getValVT().getStoreSize();
lib/Target/ARC/ARCISelLowering.cpp 381 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue);
lib/Target/ARM/ARMCallLowering.cpp 120 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
146 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
150 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
342 auto ValSize = VA.getValVT().getSizeInBits();
370 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
374 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
lib/Target/ARM/ARMFastISel.cpp 2053 MVT DestVT = RVLocs[0].getValVT();
2068 MVT CopyVT = RVLocs[0].getValVT();
2140 MVT DestVT = VA.getValVT();
lib/Target/ARM/ARMISelLowering.cpp 1995 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
4086 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4090 DAG.getValueType(VA.getValVT()));
4091 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4095 DAG.getValueType(VA.getValVT()));
4096 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4104 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
4135 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
lib/Target/AVR/AVRISelLowering.cpp 1095 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1099 DAG.getValueType(VA.getValVT()));
1100 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1104 DAG.getValueType(VA.getValVT()));
1105 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1333 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
lib/Target/BPF/BPFISelLowering.cpp 248 DAG.getValueType(VA.getValVT()));
251 DAG.getValueType(VA.getValVT()));
254 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
476 Val.getValVT(), InFlag).getValue(1);
lib/Target/Hexagon/HexagonISelLowering.cpp 279 if (RVLocs[i].getValVT() == MVT::i1) {
301 RVLocs[i].getValVT(), Glue);
385 bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
736 RegVT = VA.getValVT();
745 if (VA.getValVT() == MVT::i1) {
780 SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
lib/Target/Lanai/LanaiISelLowering.cpp 472 DAG.getValueType(VA.getValVT()));
475 DAG.getValueType(VA.getValVT()));
478 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
788 RVLocs[I].getValVT(), InFlag)
lib/Target/MSP430/MSP430ISelLowering.cpp 647 DAG.getValueType(VA.getValVT()));
650 DAG.getValueType(VA.getValVT()));
653 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
935 RVLocs[i].getValVT(), InFlag).getValue(1);
lib/Target/Mips/MipsCallLowering.cpp 183 unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
306 unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
405 CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
408 ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
lib/Target/Mips/MipsFastISel.cpp 1295 MVT CopyVT = RVLocs[0].getValVT();
1753 MVT DestVT = VA.getValVT();
lib/Target/Mips/MipsISelLowering.cpp 3129 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3378 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3382 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3387 DAG.getValueType(VA.getValVT()));
3388 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3393 DAG.getValueType(VA.getValVT()));
3394 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3408 EVT ValVT = VA.getValVT();
3502 EVT ValVT = VA.getValVT();
3560 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3561 LocVT = VA.getValVT();
lib/Target/PowerPC/PPCFastISel.cpp 1509 MVT DestVT = VA.getValVT();
lib/Target/PowerPC/PPCISelLowering.cpp 3483 EVT ValVT = VA.getValVT();
3558 unsigned ObjSize = VA.getValVT().getStoreSize();
3567 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
5197 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5201 DAG.getValueType(VA.getValVT()));
5202 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5206 DAG.getValueType(VA.getValVT()));
5207 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
lib/Target/RISCV/RISCVISelLowering.cpp 1417 State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
1423 CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
1675 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1679 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1730 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1747 EVT ValVT = VA.getValVT();
1772 assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 &&
1914 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
1925 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1934 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
2163 VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
2343 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2405 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
lib/Target/Sparc/SparcISelLowering.cpp 339 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
468 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
468 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
476 DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
500 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
510 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
510 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
511 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
512 } else if (VA.getValVT() == MVT::f128) {
605 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
614 DAG.getValueType(VA.getValVT()));
618 DAG.getValueType(VA.getValVT()));
626 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
637 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
645 DAG.getLoad(VA.getValVT(), DL, Chain,
1007 RVLocs[i].getValVT(), InFlag)
1073 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1079 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1084 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1159 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1166 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1194 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1321 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1330 DAG.getValueType(VA.getValVT()));
1334 DAG.getValueType(VA.getValVT()));
1342 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
lib/Target/SystemZ/SystemZISelLowering.cpp 1247 DAG.getValueType(VA.getValVT()));
1250 DAG.getValueType(VA.getValVT()));
1253 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
1258 assert(VA.getValVT().isVector());
1260 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
1282 assert(VA.getValVT().isVector());
1378 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1389 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
lib/Target/X86/X86CallLowering.cpp 137 unsigned ValSize = VA.getValVT().getSizeInBits();
271 unsigned ValSize = VA.getValVT().getSizeInBits();
lib/Target/X86/X86FastISel.cpp 1222 EVT DstVT = VA.getValVT();
3554 EVT CopyVT = VA.getValVT();
3567 isScalarFPTypeInSSEReg(VA.getValVT())) {
3580 if (CopyVT != VA.getValVT()) {
3581 EVT ResVT = VA.getValVT();
lib/Target/X86/X86ISelLowering.cpp 2545 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2571 assert(VA.getValVT() == MVT::v64i1 &&
2739 assert(VA.getValVT() == MVT::v64i1 &&
2741 assert(NextVA.getValVT() == VA.getValVT() &&
2741 assert(NextVA.getValVT() == VA.getValVT() &&
2863 isScalarFPTypeInSSEReg(VA.getValVT())) {
2872 assert(VA.getValVT() == MVT::v64i1 &&
2884 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2888 if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2889 if (VA.getValVT().isVector() &&
2893 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
2895 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3027 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
3028 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
3033 ValVT = VA.getValVT();
3110 ? (VA.getValVT().isVector()
3111 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3112 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3225 VA.getValVT() == MVT::v64i1 &&
3280 DAG.getValueType(VA.getValVT()));
3283 DAG.getValueType(VA.getValVT()));
3285 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3289 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3290 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3291 else if (VA.getValVT().isVector() &&
3292 VA.getValVT().getScalarType() == MVT::i1 &&
3296 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3298 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3309 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3808 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3820 assert(VA.getValVT() == MVT::v64i1 &&
lib/Target/XCore/XCoreISelLowering.cpp 1069 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),