reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
119 if (unsigned Reg = State.AllocateReg(AArch64::X18)) { 955 if (unsigned Reg = State.AllocateReg(AArch64::X15)) {gen/lib/Target/ARM/ARMGenCallingConv.inc
57 if (unsigned Reg = State.AllocateReg(ARM::R12)) { 87 if (unsigned Reg = State.AllocateReg(ARM::R10)) { 96 if (unsigned Reg = State.AllocateReg(ARM::R8)) { 259 if (unsigned Reg = State.AllocateReg(ARM::R10)) { 268 if (unsigned Reg = State.AllocateReg(ARM::R8)) { 340 if (unsigned Reg = State.AllocateReg(ARM::R10)) { 349 if (unsigned Reg = State.AllocateReg(ARM::R8)) { 503 if (unsigned Reg = State.AllocateReg(ARM::R0)) { 629 if (unsigned Reg = State.AllocateReg(ARM::R10)) { 638 if (unsigned Reg = State.AllocateReg(ARM::R8)) { 734 if (unsigned Reg = State.AllocateReg(ARM::R10)) { 743 if (unsigned Reg = State.AllocateReg(ARM::R8)) { 810 if (unsigned Reg = State.AllocateReg(ARM::R10)) { 819 if (unsigned Reg = State.AllocateReg(ARM::R8)) {gen/lib/Target/AVR/AVRGenCallingConv.inc
68 if (unsigned Reg = State.AllocateReg(AVR::R24)) {
gen/lib/Target/BPF/BPFGenCallingConv.inc 122 if (unsigned Reg = State.AllocateReg(BPF::R0)) {
gen/lib/Target/Hexagon/HexagonGenCallingConv.inc293 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 311 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) { 322 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) { 333 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) { 344 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {gen/lib/Target/PowerPC/PPCGenCallingConv.inc
163 if (unsigned Reg = State.AllocateReg(PPC::R11)) { 716 if (unsigned Reg = State.AllocateReg(PPC::R3)) { 723 if (unsigned Reg = State.AllocateReg(PPC::X3)) { 730 if (unsigned Reg = State.AllocateReg(PPC::X3)) { 737 if (unsigned Reg = State.AllocateReg(PPC::F1)) { 744 if (unsigned Reg = State.AllocateReg(PPC::F1)) { 752 if (unsigned Reg = State.AllocateReg(PPC::V2)) { 763 if (unsigned Reg = State.AllocateReg(PPC::QF1)) { 778 if (unsigned Reg = State.AllocateReg(PPC::V2)) {gen/lib/Target/SystemZ/SystemZGenCallingConv.inc
35 if (unsigned Reg = State.AllocateReg(SystemZ::R10D)) { 44 if (unsigned Reg = State.AllocateReg(SystemZ::R9D)) { 178 if (unsigned Reg = State.AllocateReg(SystemZ::R9D)) {gen/lib/Target/X86/X86GenCallingConv.inc
268 if (unsigned Reg = State.AllocateReg(X86::K1)) { 396 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 582 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 641 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 843 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 861 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 890 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 1053 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 1402 if (unsigned Reg = State.AllocateReg(X86::R10D)) { 1410 if (unsigned Reg = State.AllocateReg(X86::R10)) { 1418 if (unsigned Reg = State.AllocateReg(X86::R13)) { 1427 if (unsigned Reg = State.AllocateReg(X86::R12)) { 1437 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 1758 if (unsigned Reg = State.AllocateReg(X86::RBP)) { 1826 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 1833 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 1962 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 2109 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 2154 if (unsigned Reg = State.AllocateReg(X86::R10)) { 2162 if (unsigned Reg = State.AllocateReg(X86::R12)) { 2170 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 2425 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 2824 if (unsigned Reg = State.AllocateReg(X86::MM0)) { 3080 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3098 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3339 if (unsigned Reg = State.AllocateReg(X86::R12)) { 3419 if (unsigned Reg = State.AllocateReg(X86::R12)) { 3573 if (unsigned Reg = State.AllocateReg(X86::RAX)) {gen/lib/Target/XCore/XCoreGenCallingConv.inc
33 if (unsigned Reg = State.AllocateReg(XCore::R11)) {
lib/Target/AArch64/AArch64CallingConvention.cpp 147 State.AllocateReg(Reg);
lib/Target/AMDGPU/AMDGPUCallLowering.cpp395 CCInfo.AllocateReg(PrivateSegmentBufferReg); 401 CCInfo.AllocateReg(DispatchPtrReg); 407 CCInfo.AllocateReg(QueuePtrReg); 418 CCInfo.AllocateReg(InputPtrReg); 424 CCInfo.AllocateReg(DispatchIDReg); 430 CCInfo.AllocateReg(FlatScratchInitReg); 587 CCInfo.AllocateReg(ImplicitBufferPtrReg); 663 CCInfo.AllocateReg(AMDGPU::VGPR0); 664 CCInfo.AllocateReg(AMDGPU::VGPR1); 706 CCInfo.AllocateReg(Info->getScratchRSrcReg()); 707 CCInfo.AllocateReg(Info->getScratchWaveOffsetReg()); 708 CCInfo.AllocateReg(Info->getFrameOffsetReg());lib/Target/AMDGPU/SIISelLowering.cpp
1624 CCInfo.AllocateReg(Reg); 1632 CCInfo.AllocateReg(Reg); 1640 CCInfo.AllocateReg(Reg); 1665 Reg = CCInfo.AllocateReg(Reg); 1683 Reg = CCInfo.AllocateReg(Reg); 1764 CCInfo.AllocateReg(ImplicitBufferPtrReg); 1771 CCInfo.AllocateReg(PrivateSegmentBufferReg); 1777 CCInfo.AllocateReg(DispatchPtrReg); 1783 CCInfo.AllocateReg(QueuePtrReg); 1789 CCInfo.AllocateReg(InputPtrReg); 1798 CCInfo.AllocateReg(DispatchIDReg); 1804 CCInfo.AllocateReg(FlatScratchInitReg); 1820 CCInfo.AllocateReg(Reg); 1826 CCInfo.AllocateReg(Reg); 1832 CCInfo.AllocateReg(Reg); 1838 CCInfo.AllocateReg(Reg); 1859 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg); 2065 CCInfo.AllocateReg(AMDGPU::VGPR0); 2066 CCInfo.AllocateReg(AMDGPU::VGPR1); 2223 CCInfo.AllocateReg(Info->getScratchRSrcReg()); 2224 CCInfo.AllocateReg(Info->getScratchWaveOffsetReg()); 2225 CCInfo.AllocateReg(Info->getFrameOffsetReg());lib/Target/ARM/ARMCallingConv.cpp
95 unsigned T = State.AllocateReg(LoRegList[i]); 209 State.AllocateReg(RegList[RegIdx++]); 252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); 263 State.AllocateReg(Reg);lib/Target/Hexagon/HexagonISelLowering.cpp
143 State.AllocateReg(ArgRegs[RegNum]);
lib/Target/Mips/MipsISelLowering.cpp2799 State.AllocateReg(Mips::A1); 2801 State.AllocateReg(Mips::A3);lib/Target/PowerPC/PPCCallingConv.cpp
49 State.AllocateReg(ArgRegs[RegNum]); 74 State.AllocateReg(ArgRegs[RegNum + i]); 98 State.AllocateReg(ArgRegs[RegNum]); 127 unsigned T = State.AllocateReg(LoRegList[i]);lib/Target/X86/X86CallingConv.cpp
53 unsigned Reg = State.AllocateReg(AvailableRegs[I]); 104 unsigned AssigedReg = State.AllocateReg(Reg); 282 It.convertToReg(State.AllocateReg(RegList[FirstFree++]));