|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenGICombiner.inc 64 DisabledRules.set(I);
70 DisabledRules.set(I.getValue());
include/llvm/ADT/SparseBitVector.h 534 set(Idx);
include/llvm/Analysis/BlockFrequencyInfoImpl.h 1168 IsIrrLoopHeader.set(Loop.Nodes[H].Index);
include/llvm/CodeGen/LiveVariables.h 303 void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
include/llvm/DebugInfo/PDB/Native/HashTable.h 292 Present.set(Entry.index());
lib/CodeGen/LiveDebugValues.cpp 422 VarLocs.set(VarLocID);
822 KillSet.set(ID);
831 KillSet.set(ID);
950 KillSet.set(ID);
1184 KillSet.set(ID);
1209 Pending.set(ID);
1210 ILS.set(ID);
lib/CodeGen/LiveIntervalUnion.cpp 98 VisitedVRegs.set(SI.value()->reg);
lib/CodeGen/LiveVariables.cpp 112 VRInfo.AliveBlocks.set(BBNum);
778 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
806 VI.AliveBlocks.set(NumNew);
lib/CodeGen/MachineSink.cpp 977 RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags.
lib/DebugInfo/PDB/Native/HashTable.cpp 41 V.set((I * 32) + Idx);
lib/Target/AMDGPU/SIMachineFunctionInfo.h 455 void ReserveWWMRegister(unsigned reg) { WWMReservedRegs.set(reg); }
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1680 LoadDepRegs.set(Def.getReg());
1763 LoadDepRegs.set(Def.getReg());
lib/Transforms/Scalar/NewGVN.cpp 2806 RevisitOnReachabilityChange[PHIBlock].set(InstrToDFSNum(I));
2845 RevisitOnReachabilityChange[PHIBlock].set(InstrToDFSNum(I));
2996 RevisitOnReachabilityChange[B].set(End);
unittests/ADT/SparseBitVectorTest.cpp 20 Vec.set(5);
34 Vec.set(5);
39 Vec.set(1337);
44 Vec.set(1337);
59 Vec.set(1);
60 Other.set(1);
65 Vec.set(5);
67 Other.set(6);
72 Vec.set(5);
74 Other.set(225);
79 Vec.set(225);
81 Other.set(5);
89 Vec.set(23);
90 Vec.set(234);
96 Vec.set(17);
97 Vec.set(256);
103 Vec.set(56);
104 Vec.set(517);
110 Vec.set(99);
111 Vec.set(333);
117 Vec.set(28);
118 Vec.set(43);
123 Vec.set(42);
124 Vec.set(567);
125 Other.set(55);
126 Other.set(567);
132 Vec.set(19);
133 Vec.set(21);
135 Other.set(19);
136 Other.set(31);
142 Vec.set(1);
144 Other.set(59);
145 Other.set(75);
152 Vec.set(1);
156 Vec.set(2);
160 Vec.set(0);
161 Vec.set(3);
173 Vec.set(500);
174 Vec.set(2000);
175 Vec.set(3000);
176 Vec.set(4000);
utils/TableGen/CodeGenRegisters.cpp 435 RegUnits.set(Unit);
436 AR->RegUnits.set(Unit);
443 RegUnits.set(RegBank.newRegUnit(this));
utils/TableGen/CodeGenRegisters.h 254 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }