|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
gen/lib/Target/X86/X86GenRegisterInfo.inc 4364 extern const TargetRegisterClass GR32RegClass;
References
gen/lib/Target/X86/X86GenFastISel.inc 200 return fastEmitInst_r(X86::MOVZX32rr8, &X86::GR32RegClass, Op0, Op0IsKill);
387 return fastEmitInst_r(X86::VMOVSS2DIZrr, &X86::GR32RegClass, Op0, Op0IsKill);
390 return fastEmitInst_r(X86::MOVSS2DIrr, &X86::GR32RegClass, Op0, Op0IsKill);
393 return fastEmitInst_r(X86::VMOVSS2DIrr, &X86::GR32RegClass, Op0, Op0IsKill);
474 return fastEmitInst_r(X86::JMP32r, &X86::GR32RegClass, Op0, Op0IsKill);
502 return fastEmitInst_r(X86::BSWAP32r, &X86::GR32RegClass, Op0, Op0IsKill);
534 return fastEmitInst_r(X86::LZCNT32rr, &X86::GR32RegClass, Op0, Op0IsKill);
632 return fastEmitInst_r(X86::POPCNT32rr, &X86::GR32RegClass, Op0, Op0IsKill);
790 return fastEmitInst_r(X86::TZCNT32rr, &X86::GR32RegClass, Op0, Op0IsKill);
824 return fastEmitInst_r(X86::BSF32rr, &X86::GR32RegClass, Op0, Op0IsKill);
1033 return fastEmitInst_r(X86::VCVTTSS2SIZrr, &X86::GR32RegClass, Op0, Op0IsKill);
1036 return fastEmitInst_r(X86::CVTTSS2SIrr, &X86::GR32RegClass, Op0, Op0IsKill);
1039 return fastEmitInst_r(X86::VCVTTSS2SIrr, &X86::GR32RegClass, Op0, Op0IsKill);
1067 return fastEmitInst_r(X86::VCVTTSD2SIZrr, &X86::GR32RegClass, Op0, Op0IsKill);
1070 return fastEmitInst_r(X86::CVTTSD2SIrr, &X86::GR32RegClass, Op0, Op0IsKill);
1073 return fastEmitInst_r(X86::VCVTTSD2SIrr, &X86::GR32RegClass, Op0, Op0IsKill);
1121 return fastEmitInst_r(X86::VCVTTSS2USIZrr, &X86::GR32RegClass, Op0, Op0IsKill);
1143 return fastEmitInst_r(X86::VCVTTSD2USIZrr, &X86::GR32RegClass, Op0, Op0IsKill);
1381 return fastEmitInst_r(X86::MOVSX32rr8, &X86::GR32RegClass, Op0, Op0IsKill);
1397 return fastEmitInst_r(X86::MOVSX32rr16, &X86::GR32RegClass, Op0, Op0IsKill);
2251 return fastEmitInst_r(X86::MOVZX32rr8, &X86::GR32RegClass, Op0, Op0IsKill);
2257 return fastEmitInst_r(X86::MOVZX32rr16, &X86::GR32RegClass, Op0, Op0IsKill);
2527 return fastEmitInst_r(X86::RETPOLINE_CALL32, &X86::GR32RegClass, Op0, Op0IsKill);
2530 return fastEmitInst_r(X86::CALL32r, &X86::GR32RegClass, Op0, Op0IsKill);
3031 return fastEmitInst_r(X86::VCVTSS2SIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3034 return fastEmitInst_r(X86::CVTSS2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3037 return fastEmitInst_r(X86::VCVTSS2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3065 return fastEmitInst_r(X86::VCVTSD2SIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3068 return fastEmitInst_r(X86::CVTSD2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3071 return fastEmitInst_r(X86::VCVTSD2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3109 return fastEmitInst_r(X86::VCVTSS2USIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3131 return fastEmitInst_r(X86::VCVTSD2USIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3599 return fastEmitInst_r(X86::VCVTTSS2SIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3602 return fastEmitInst_r(X86::CVTTSS2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3605 return fastEmitInst_r(X86::VCVTTSS2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3633 return fastEmitInst_r(X86::VCVTTSD2SIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3636 return fastEmitInst_r(X86::CVTTSD2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3639 return fastEmitInst_r(X86::VCVTTSD2SIrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3677 return fastEmitInst_r(X86::VCVTTSS2SIZrrb_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3699 return fastEmitInst_r(X86::VCVTTSD2SIZrrb_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3731 return fastEmitInst_r(X86::VCVTTSS2USIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3753 return fastEmitInst_r(X86::VCVTTSD2USIZrr_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3785 return fastEmitInst_r(X86::VCVTTSS2USIZrrb_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3807 return fastEmitInst_r(X86::VCVTTSD2USIZrrb_Int, &X86::GR32RegClass, Op0, Op0IsKill);
3868 return fastEmitInst_r(X86::EH_RETURN, &X86::GR32RegClass, Op0, Op0IsKill);
4125 return fastEmitInst_r(X86::MMX_MOVD64grr, &X86::GR32RegClass, Op0, Op0IsKill);
4220 return fastEmitInst_r(X86::PMOVMSKBrr, &X86::GR32RegClass, Op0, Op0IsKill);
4223 return fastEmitInst_r(X86::VPMOVMSKBrr, &X86::GR32RegClass, Op0, Op0IsKill);
4232 return fastEmitInst_r(X86::VPMOVMSKBYrr, &X86::GR32RegClass, Op0, Op0IsKill);
4241 return fastEmitInst_r(X86::MOVMSKPSrr, &X86::GR32RegClass, Op0, Op0IsKill);
4244 return fastEmitInst_r(X86::VMOVMSKPSrr, &X86::GR32RegClass, Op0, Op0IsKill);
4253 return fastEmitInst_r(X86::VMOVMSKPSYrr, &X86::GR32RegClass, Op0, Op0IsKill);
4262 return fastEmitInst_r(X86::MOVMSKPDrr, &X86::GR32RegClass, Op0, Op0IsKill);
4265 return fastEmitInst_r(X86::VMOVMSKPDrr, &X86::GR32RegClass, Op0, Op0IsKill);
4274 return fastEmitInst_r(X86::VMOVMSKPDYrr, &X86::GR32RegClass, Op0, Op0IsKill);
4283 return fastEmitInst_r(X86::MOVMSKPSrr, &X86::GR32RegClass, Op0, Op0IsKill);
4286 return fastEmitInst_r(X86::VMOVMSKPSrr, &X86::GR32RegClass, Op0, Op0IsKill);
4295 return fastEmitInst_r(X86::VMOVMSKPSYrr, &X86::GR32RegClass, Op0, Op0IsKill);
4304 return fastEmitInst_r(X86::MOVMSKPDrr, &X86::GR32RegClass, Op0, Op0IsKill);
4307 return fastEmitInst_r(X86::VMOVMSKPDrr, &X86::GR32RegClass, Op0, Op0IsKill);
4316 return fastEmitInst_r(X86::VMOVMSKPDYrr, &X86::GR32RegClass, Op0, Op0IsKill);
4507 return fastEmitInst_r(X86::JMP32r_NT, &X86::GR32RegClass, Op0, Op0IsKill);
4545 return fastEmitInst_r(X86::CALL32r_NT, &X86::GR32RegClass, Op0, Op0IsKill);
4843 return fastEmitInst_r(X86::SEG_ALLOCA_32, &X86::GR32RegClass, Op0, Op0IsKill);
5877 return fastEmitInst_r(X86::WIN_ALLOCA_32, &X86::GR32RegClass, Op0, Op0IsKill);
6004 return fastEmitInst_rr(X86::ADD32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6196 return fastEmitInst_rr(X86::AND32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6965 return fastEmitInst_rr(X86::IMUL32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7203 return fastEmitInst_rr(X86::OR32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
8155 return fastEmitInst_rr(X86::SUB32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
8829 return fastEmitInst_rr(X86::XOR32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9378 return fastEmitInst_rr(X86::BEXTR32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9411 return fastEmitInst_rr(X86::BT32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9435 return fastEmitInst_rr(X86::BZHI32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9474 return fastEmitInst_rr(X86::CMP32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
13635 return fastEmitInst_ri(X86::ADD32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13664 return fastEmitInst_ri(X86::AND32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13682 return fastEmitInst_ri(X86::VPEXTRDZrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13685 return fastEmitInst_ri(X86::PEXTRDrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13688 return fastEmitInst_ri(X86::VPEXTRDrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13727 return fastEmitInst_ri(X86::IMUL32rri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13755 return fastEmitInst_ri(X86::OR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13773 return fastEmitInst_ri(X86::SHLDROT32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13801 return fastEmitInst_ri(X86::RORX32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13804 return fastEmitInst_ri(X86::SHRDROT32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13846 return fastEmitInst_ri(X86::SHL32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13882 return fastEmitInst_ri(X86::SAR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13918 return fastEmitInst_ri(X86::SHR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13954 return fastEmitInst_ri(X86::SUB32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
13983 return fastEmitInst_ri(X86::XOR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14001 return fastEmitInst_ri(X86::BEXTRI32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14024 return fastEmitInst_ri(X86::BT32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14048 return fastEmitInst_ri(X86::VPEXTRBZrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14051 return fastEmitInst_ri(X86::PEXTRBrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14054 return fastEmitInst_ri(X86::VPEXTRBrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14072 return fastEmitInst_ri(X86::VPEXTRWZrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14075 return fastEmitInst_ri(X86::PEXTRWrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14078 return fastEmitInst_ri(X86::VPEXTRWrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14362 return fastEmitInst_ri(X86::ADD32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14377 return fastEmitInst_ri(X86::AND32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14392 return fastEmitInst_ri(X86::IMUL32rri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14407 return fastEmitInst_ri(X86::OR32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14422 return fastEmitInst_ri(X86::SUB32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
14437 return fastEmitInst_ri(X86::XOR32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/X86/X86GenRegisterInfo.inc 5397 &X86::GR32RegClass,
5411 &X86::GR32RegClass,
5429 &X86::GR32RegClass,
5455 &X86::GR32RegClass,
5467 &X86::GR32RegClass,
5477 &X86::GR32RegClass,
5491 &X86::GR32RegClass,
5506 &X86::GR32RegClass,
5516 &X86::GR32RegClass,
5528 &X86::GR32RegClass,
5541 &X86::GR32RegClass,
5556 &X86::GR32RegClass,
5568 &X86::GR32RegClass,
5585 &X86::GR32RegClass,
5600 &X86::GR32RegClass,
5617 &X86::GR32RegClass,
5631 &X86::GR32RegClass,
5643 &X86::GR32RegClass,
5657 &X86::GR32RegClass,
5674 &X86::GR32RegClass,
7736 &X86::GR32RegClass,
lib/Target/X86/X86AsmPrinter.cpp 396 !X86::GR32RegClass.contains(Reg) &&
lib/Target/X86/X86DomainReassignment.cpp 46 X86::GR32RegClass.hasSubClassEq(RC) ||
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC))
lib/Target/X86/X86FastISel.cpp 787 RC = &X86::GR32RegClass;
1438 ResultReg = createResultReg(&X86::GR32RegClass);
1550 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1561 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1607 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1763 OpReg = createResultReg(&X86::GR32RegClass);
1802 RC = &X86::GR32RegClass;
1893 { &X86::GR32RegClass, X86::EAX, X86::EDX, {
1951 unsigned Zero32 = createResultReg(&X86::GR32RegClass);
2109 CondReg = createResultReg(&X86::GR32RegClass);
2327 CondReg = createResultReg(&X86::GR32RegClass);
2637 ResultReg = createResultReg(&X86::GR32RegClass);
2684 case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break;
3690 unsigned SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass);
lib/Target/X86/X86FixupSetCC.cpp 137 ? &X86::GR32RegClass
lib/Target/X86/X86FlagsCopyLowering.cpp 934 NewReg = MRI->createVirtualRegister(&X86::GR32RegClass);
937 if (&SetBRC == &X86::GR32RegClass)
978 Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass);
lib/Target/X86/X86FrameLowering.cpp 2017 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2033 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2081 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2114 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2195 X86::GR32RegClass.contains(Reg))
2212 !X86::GR32RegClass.contains(Reg))
lib/Target/X86/X86ISelLowering.cpp 180 addRegisterClass(MVT::i32, &X86::GR32RegClass);
2262 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2750 const TargetRegisterClass *RC = &X86::GR32RegClass;
3239 RC = &X86::GR32RegClass;
30817 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
30905 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
31068 Register OReg = MRI->createVirtualRegister(&X86::GR32RegClass);
31264 Register OldCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
31269 Register NewCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
45760 RC.hasSuperClassEq(&X86::GR32RegClass) ||
45827 return std::make_pair(0U, &X86::GR32RegClass);
45855 return std::make_pair(0U, &X86::GR32RegClass);
45968 return std::make_pair(0U, &X86::GR32RegClass);
46049 : Size == 32 ? (is64Bit ? &X86::GR32RegClass : &X86::GR32_NOREXRegClass)
lib/Target/X86/X86InstrInfo.cpp 710 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
781 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2851 X86::GR32RegClass.hasSubClassEq(RC) ||
2902 if (X86::GR32RegClass.contains(DestReg))
2915 if (X86::GR32RegClass.contains(SrcReg))
2948 if (X86::GR32RegClass.contains(DestReg) &&
2956 X86::GR32RegClass.contains(SrcReg))
2974 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3086 if (X86::GR32RegClass.hasSubClassEq(RC))
4600 } else if (X86::GR32RegClass.contains(Reg)) {
7768 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7929 : &X86::GR32RegClass);
lib/Target/X86/X86InstructionSelector.cpp 175 return &X86::GR32RegClass;
204 if (RC == &X86::GR32RegClass) {
219 if (X86::GR32RegClass.contains(Reg))
220 return &X86::GR32RegClass;
745 } else if (DstRC == &X86::GR32RegClass) {
1108 if (!RBI.constrainGenericRegister(CarryInReg, X86::GR32RegClass, MRI))
1130 !RBI.constrainGenericRegister(CarryOutReg, X86::GR32RegClass, MRI))
1652 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
lib/Target/X86/X86MachineFunctionInfo.cpp 25 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
lib/Target/X86/X86RegisterBankInfo.cpp 48 X86::GR32RegClass.hasSubClassEq(&RC) ||
lib/Target/X86/X86RegisterInfo.cpp 199 return &X86::GR32RegClass;
244 return &X86::GR32RegClass;
254 return &X86::GR32RegClass;
758 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
lib/Target/X86/X86SpeculativeLoadHardening.cpp 480 Register PredStateSubReg = MRI->createVirtualRegister(&X86::GR32RegClass);
1881 Register Reg = MRI->createVirtualRegister(&X86::GR32RegClass);
2261 &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass,
tools/llvm-exegesis/lib/X86/Target.cpp 670 if (X86::GR32RegClass.contains(Reg))